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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_iic___config.html">XIic_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the device.  <a href="struct_x_iic___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_iic_stats.html">XIicStats</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight"><a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> statistics.  <a href="struct_x_iic_stats.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_iic.html">XIic</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> driver instance data.  <a href="struct_x_iic.html#details">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gace6af337aea33e4f162897b40591e0ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gace6af337aea33e4f162897b40591e0ac">XII_ADDR_TO_SEND_TYPE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gace6af337aea33e4f162897b40591e0ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus address of slave device.  <a href="#gace6af337aea33e4f162897b40591e0ac">More...</a><br/></td></tr>
<tr class="separator:gace6af337aea33e4f162897b40591e0ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3f6ec08afcad8f35f9ee2c9e2531366"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab3f6ec08afcad8f35f9ee2c9e2531366">XII_ADDR_TO_RESPOND_TYPE</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gab3f6ec08afcad8f35f9ee2c9e2531366"><td class="mdescLeft">&#160;</td><td class="mdescRight">This device's bus address as slave.  <a href="#gab3f6ec08afcad8f35f9ee2c9e2531366">More...</a><br/></td></tr>
<tr class="separator:gab3f6ec08afcad8f35f9ee2c9e2531366"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab81f7edf097fc4a885fd6134a288a817"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gab81f7edf097fc4a885fd6134a288a817"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used to specify whether to do Read or a Write operation on IIC bus.  <a href="#gab81f7edf097fc4a885fd6134a288a817">More...</a><br/></td></tr>
<tr class="separator:gab81f7edf097fc4a885fd6134a288a817"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write operation on the IIC bus.  <a href="#ga8bb1f3ab452d41daf06eff8d61048fe8">More...</a><br/></td></tr>
<tr class="separator:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">XIIC_MASTER_ROLE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave.  <a href="#gaa0040c82cb3f8c0bbff61cbbad86e1ac">More...</a><br/></td></tr>
<tr class="separator:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85bbbc139ce96e43b2f1f947d0652539"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga85bbbc139ce96e43b2f1f947d0652539">XIIC_SLAVE_ROLE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga85bbbc139ce96e43b2f1f947d0652539"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave on the IIC bus.  <a href="#ga85bbbc139ce96e43b2f1f947d0652539">More...</a><br/></td></tr>
<tr class="separator:ga85bbbc139ce96e43b2f1f947d0652539"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacdf6b790e752c7f789c81ee4721bafe8">XIIC_STOP</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gacdf6b790e752c7f789c81ee4721bafe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start.  <a href="#gacdf6b790e752c7f789c81ee4721bafe8">More...</a><br/></td></tr>
<tr class="separator:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae2c7104aa187b965ff0adbe3d4e1bccb">XIIC_REPEATED_START</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Donot Send a stop on the IIC bus after the current data transfer.  <a href="#gae2c7104aa187b965ff0adbe3d4e1bccb">More...</a><br/></td></tr>
<tr class="separator:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XIic_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab28be58b11c65ecc54fc2f0c300412c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from the specified IIC device register.  <a href="#gab28be58b11c65ecc54fc2f0c300412c1">More...</a><br/></td></tr>
<tr class="separator:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the specified IIC device register.  <a href="#ga7a9318f43afc81c1dbd30a27587ba51d">More...</a><br/></td></tr>
<tr class="separator:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17d0df7020d5264d20bbc36d276e276e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>, 0)</td></tr>
<tr class="memdesc:ga17d0df7020d5264d20bbc36d276e276e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables all interrupts for the device by writing to the Global interrupt enable register.  <a href="#ga17d0df7020d5264d20bbc36d276e276e">More...</a><br/></td></tr>
<tr class="separator:ga17d0df7020d5264d20bbc36d276e276e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga7071fcf4cf60d65fd862653fa34faa21"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the global interrupt enable register to enable interrupts from the device.  <a href="#ga7071fcf4cf60d65fd862653fa34faa21">More...</a><br/></td></tr>
<tr class="separator:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa839067df3b55f3181db24ebd8db3187"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa839067df3b55f3181db24ebd8db3187">XIic_IsIntrGlobalEnabled</a>(BaseAddress)</td></tr>
<tr class="memdesc:gaa839067df3b55f3181db24ebd8db3187"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function determines if interrupts are enabled at the global level by reading the global interrupt register.  <a href="#gaa839067df3b55f3181db24ebd8db3187">More...</a><br/></td></tr>
<tr class="separator:gaa839067df3b55f3181db24ebd8db3187"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bc448908013aceb690c84fdbb7d66a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a>(BaseAddress, Status)&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>, (Status))</td></tr>
<tr class="memdesc:ga3bc448908013aceb690c84fdbb7d66a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Interrupt status register to the specified value.  <a href="#ga3bc448908013aceb690c84fdbb7d66a8">More...</a><br/></td></tr>
<tr class="separator:ga3bc448908013aceb690c84fdbb7d66a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>)</td></tr>
<tr class="memdesc:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the contents of the Interrupt Status Register.  <a href="#gaf69a6487ad62b105aa3bb8d0e25b7fe7">More...</a><br/></td></tr>
<tr class="separator:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2f926a076e9a6b80bea46664d2e55ee9">XIic_WriteIier</a>(BaseAddress, Enable)&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>, (Enable))</td></tr>
<tr class="memdesc:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the contents of the Interrupt Enable Register.  <a href="#ga2f926a076e9a6b80bea46664d2e55ee9">More...</a><br/></td></tr>
<tr class="separator:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaee17ffc86a8270abeb1319e8c67ccce5">XIic_ReadIier</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>)</td></tr>
<tr class="memdesc:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the Interrupt Enable Register contents.  <a href="#gaee17ffc86a8270abeb1319e8c67ccce5">More...</a><br/></td></tr>
<tr class="separator:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>(BaseAddress, InterruptMask)</td></tr>
<tr class="memdesc:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the specified interrupt in the Interrupt status register.  <a href="#gaf8fa6ffa77af5942fa1dbd1b5a666d55">More...</a><br/></td></tr>
<tr class="separator:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89d095e79795958bcbc15238a7bbfa32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga89d095e79795958bcbc15238a7bbfa32">XIic_Send7BitAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="memdesc:ga89d095e79795958bcbc15238a7bbfa32"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address for a 7 bit address during both read and write operations.  <a href="#ga89d095e79795958bcbc15238a7bbfa32">More...</a><br/></td></tr>
<tr class="separator:ga89d095e79795958bcbc15238a7bbfa32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="memdesc:ga81d32f9fd29736e9f9c7ef345527386b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address for a 7 bit address during both read and write operations.  <a href="#ga81d32f9fd29736e9f9c7ef345527386b">More...</a><br/></td></tr>
<tr class="separator:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga682d21ed5020daa5b5a863bbffb35cc5">XIic_DynSendStartStopAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="memdesc:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address, start and stop for a 7 bit address during both write operations.  <a href="#ga682d21ed5020daa5b5a863bbffb35cc5">More...</a><br/></td></tr>
<tr class="separator:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga22446f72b705b950e4b485ab9cdd2ae6">XIic_DynSendStop</a>(BaseAddress, ByteCount)</td></tr>
<tr class="memdesc:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends a stop condition on IIC bus for Dynamic logic.  <a href="#ga22446f72b705b950e4b485ab9cdd2ae6">More...</a><br/></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga85db866c44d23a4c6e985f2c6c647053"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga85db866c44d23a4c6e985f2c6c647053">XIic_Handler</a> )(void *CallBackRef, int ByteCount)</td></tr>
<tr class="memdesc:ga85db866c44d23a4c6e985f2c6c647053"><td class="mdescLeft">&#160;</td><td class="mdescRight">This callback function data type is defined to handle the asynchronous processing of sent and received data of the IIC driver.  <a href="#ga85db866c44d23a4c6e985f2c6c647053">More...</a><br/></td></tr>
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<tr class="memitem:gac96e3f6975be1bdb8fe5956812855962"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac96e3f6975be1bdb8fe5956812855962">XIic_StatusHandler</a> )(void *CallBackRef, int StatusEvent)</td></tr>
<tr class="memdesc:gac96e3f6975be1bdb8fe5956812855962"><td class="mdescLeft">&#160;</td><td class="mdescRight">This callback function data type is defined to handle the asynchronous processing of status events of the IIC driver.  <a href="#gac96e3f6975be1bdb8fe5956812855962">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga301f08e1fa6e74bf4c2885702bf0ff70"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga301f08e1fa6e74bf4c2885702bf0ff70">XIic_CfgInitialize</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, <a class="el" href="struct_x_iic___config.html">XIic_Config</a> *Config, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ga301f08e1fa6e74bf4c2885702bf0ff70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance.  <a href="#ga301f08e1fa6e74bf4c2885702bf0ff70">More...</a><br/></td></tr>
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<tr class="memitem:ga5f4e497710a9c3719f27d40faa74a10f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga5f4e497710a9c3719f27d40faa74a10f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts the IIC device and driver by enabling the proper interrupts such that data may be sent and received on the IIC bus.  <a href="#ga5f4e497710a9c3719f27d40faa74a10f">More...</a><br/></td></tr>
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<tr class="memitem:gaaa989e0128057bf11803825d774d496f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaaa989e0128057bf11803825d774d496f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function stops the IIC device and driver such that data is no longer sent or received on the IIC bus.  <a href="#gaaa989e0128057bf11803825d774d496f">More...</a><br/></td></tr>
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<tr class="memitem:ga237935ed7fb41369f52d1d8a4f6fe2a6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga237935ed7fb41369f52d1d8a4f6fe2a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets the IIC device.  <a href="#ga237935ed7fb41369f52d1d8a4f6fe2a6">More...</a><br/></td></tr>
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<tr class="memitem:gad944f42c3d9972fc2c986a7eed726297"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, int AddressType, int Address)</td></tr>
<tr class="memdesc:gad944f42c3d9972fc2c986a7eed726297"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the bus addresses.  <a href="#gad944f42c3d9972fc2c986a7eed726297">More...</a><br/></td></tr>
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<tr class="memitem:ga3e8f77e5df8d92a4b27627e03b5e1807"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3e8f77e5df8d92a4b27627e03b5e1807">XIic_GetAddress</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, int AddressType)</td></tr>
<tr class="memdesc:ga3e8f77e5df8d92a4b27627e03b5e1807"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the addresses for the IIC device driver.  <a href="#ga3e8f77e5df8d92a4b27627e03b5e1807">More...</a><br/></td></tr>
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<tr class="memitem:gafe4e886e72abb9d860a6cb83c84c74a1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafe4e886e72abb9d860a6cb83c84c74a1">XIic_SetGpOutput</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 OutputValue)</td></tr>
<tr class="memdesc:gafe4e886e72abb9d860a6cb83c84c74a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the contents of the General Purpose Output register for the IIC device driver.  <a href="#gafe4e886e72abb9d860a6cb83c84c74a1">More...</a><br/></td></tr>
<tr class="separator:gafe4e886e72abb9d860a6cb83c84c74a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4108f79d22b71e2455844a8487b1a776"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4108f79d22b71e2455844a8487b1a776">XIic_GetGpOutput</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *OutputValuePtr)</td></tr>
<tr class="memdesc:ga4108f79d22b71e2455844a8487b1a776"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the contents of the General Purpose Output register for the IIC device driver.  <a href="#ga4108f79d22b71e2455844a8487b1a776">More...</a><br/></td></tr>
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<tr class="memitem:gaa4b84f9d58cbd40d2633140d79e2aed4"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa4b84f9d58cbd40d2633140d79e2aed4">XIic_IsSlave</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa4b84f9d58cbd40d2633140d79e2aed4"><td class="mdescLeft">&#160;</td><td class="mdescRight">A function to determine if the device is currently addressed as a slave.  <a href="#gaa4b84f9d58cbd40d2633140d79e2aed4">More...</a><br/></td></tr>
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<tr class="memitem:ga86b4b2b307df26df2ecac39337c78bed"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga86b4b2b307df26df2ecac39337c78bed">XIic_SetRecvHandler</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, void *CallBackRef, <a class="el" href="group___overview.html#ga85db866c44d23a4c6e985f2c6c647053">XIic_Handler</a> FuncPtr)</td></tr>
<tr class="memdesc:ga86b4b2b307df26df2ecac39337c78bed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the receive callback function, the receive handler, which the driver calls when it finishes receiving data.  <a href="#ga86b4b2b307df26df2ecac39337c78bed">More...</a><br/></td></tr>
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<tr class="memitem:gad33428830e9016ef50c1deae59d1e604"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad33428830e9016ef50c1deae59d1e604">XIic_SetSendHandler</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, void *CallBackRef, <a class="el" href="group___overview.html#ga85db866c44d23a4c6e985f2c6c647053">XIic_Handler</a> FuncPtr)</td></tr>
<tr class="memdesc:gad33428830e9016ef50c1deae59d1e604"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the send callback function, the send handler, which the driver calls when it receives confirmation of sent data.  <a href="#gad33428830e9016ef50c1deae59d1e604">More...</a><br/></td></tr>
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<tr class="memitem:gaa74a6884f6dfc826a10768d7d0333991"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa74a6884f6dfc826a10768d7d0333991">XIic_SetStatusHandler</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, void *CallBackRef, <a class="el" href="group___overview.html#gac96e3f6975be1bdb8fe5956812855962">XIic_StatusHandler</a> FuncPtr)</td></tr>
<tr class="memdesc:gaa74a6884f6dfc826a10768d7d0333991"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the status callback function, the status handler, which the driver calls when it encounters conditions which are not data related.  <a href="#gaa74a6884f6dfc826a10768d7d0333991">More...</a><br/></td></tr>
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<tr class="memitem:gad36c610ec3139cef71f3795f9ce81308"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad36c610ec3139cef71f3795f9ce81308">XIic_Initialize</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u16 DeviceId)</td></tr>
<tr class="memdesc:gad36c610ec3139cef71f3795f9ce81308"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance.  <a href="#gad36c610ec3139cef71f3795f9ce81308">More...</a><br/></td></tr>
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<tr class="memitem:ga1dcc65dd7cb7863bf6769aed5d785304"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_iic___config.html">XIic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1dcc65dd7cb7863bf6769aed5d785304">XIic_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga1dcc65dd7cb7863bf6769aed5d785304"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the unique device ID.  <a href="#ga1dcc65dd7cb7863bf6769aed5d785304">More...</a><br/></td></tr>
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<tr class="memitem:ga50c5aa4448e8993c80ef7b6a87b1aaea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:ga50c5aa4448e8993c80ef7b6a87b1aaea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> driver.  <a href="#ga50c5aa4448e8993c80ef7b6a87b1aaea">More...</a><br/></td></tr>
<tr class="separator:ga50c5aa4448e8993c80ef7b6a87b1aaea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga337bf0d322d4a7d9b4f8baa30e00ab45"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *RxMsgPtr, int ByteCount)</td></tr>
<tr class="memdesc:ga337bf0d322d4a7d9b4f8baa30e00ab45"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives data as a master from a slave device on the IIC bus.  <a href="#ga337bf0d322d4a7d9b4f8baa30e00ab45">More...</a><br/></td></tr>
<tr class="separator:ga337bf0d322d4a7d9b4f8baa30e00ab45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga977382e8a20bd5e690229f82af2e7603"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *TxMsgPtr, int ByteCount)</td></tr>
<tr class="memdesc:ga977382e8a20bd5e690229f82af2e7603"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends data as a master on the IIC bus.  <a href="#ga977382e8a20bd5e690229f82af2e7603">More...</a><br/></td></tr>
<tr class="separator:ga977382e8a20bd5e690229f82af2e7603"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d7985d95cd029ab0b0f2a5ccc614793"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *RxMsgPtr, u8 ByteCount)</td></tr>
<tr class="memdesc:ga4d7985d95cd029ab0b0f2a5ccc614793"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives data as a master from a slave device on the IIC bus.  <a href="#ga4d7985d95cd029ab0b0f2a5ccc614793">More...</a><br/></td></tr>
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<tr class="memitem:gac4c6388d0db3b08ddcd47f0b2459ff3c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *TxMsgPtr, u8 ByteCount)</td></tr>
<tr class="memdesc:gac4c6388d0db3b08ddcd47f0b2459ff3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends data as a Dynamic master on the IIC bus.  <a href="#gac4c6388d0db3b08ddcd47f0b2459ff3c">More...</a><br/></td></tr>
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<tr class="memitem:ga543dde34d5a2f34269641ec3ab1bfdfe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga543dde34d5a2f34269641ec3ab1bfdfe">XIic_SlaveInclude</a> (void)</td></tr>
<tr class="memdesc:ga543dde34d5a2f34269641ec3ab1bfdfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function includes slave code such that slave events will be processed.  <a href="#ga543dde34d5a2f34269641ec3ab1bfdfe">More...</a><br/></td></tr>
<tr class="separator:ga543dde34d5a2f34269641ec3ab1bfdfe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25dc714d97f71049154461e1ff16bcad"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *RxMsgPtr, int ByteCount)</td></tr>
<tr class="memdesc:ga25dc714d97f71049154461e1ff16bcad"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends data as a slave on the IIC bus and should not be called until an event has occurred that indicates the device has been selected by a master attempting read from the slave (XII_MASTER_READ_EVENT).  <a href="#ga25dc714d97f71049154461e1ff16bcad">More...</a><br/></td></tr>
<tr class="separator:ga25dc714d97f71049154461e1ff16bcad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24873473751e355c82bb074a0d42ddbc"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u8 *TxMsgPtr, int ByteCount)</td></tr>
<tr class="memdesc:ga24873473751e355c82bb074a0d42ddbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends data as a slave on the IIC bus and should not be called until an event has occurred that indicates the device has been selected by a master attempting read from the slave (XII_MASTER_READ_EVENT).  <a href="#ga24873473751e355c82bb074a0d42ddbc">More...</a><br/></td></tr>
<tr class="separator:ga24873473751e355c82bb074a0d42ddbc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7a801efedbe489ba0e984dbf8f6daa4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae7a801efedbe489ba0e984dbf8f6daa4">XIic_GetStats</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, <a class="el" href="struct_x_iic_stats.html">XIicStats</a> *StatsPtr)</td></tr>
<tr class="memdesc:gae7a801efedbe489ba0e984dbf8f6daa4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets a copy of the statistics for an IIC device.  <a href="#gae7a801efedbe489ba0e984dbf8f6daa4">More...</a><br/></td></tr>
<tr class="separator:gae7a801efedbe489ba0e984dbf8f6daa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf56beeeacad67c0d24ad330ce5c42f90"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf56beeeacad67c0d24ad330ce5c42f90">XIic_ClearStats</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf56beeeacad67c0d24ad330ce5c42f90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clears the statistics for the IIC device by zeroing all counts.  <a href="#gaf56beeeacad67c0d24ad330ce5c42f90">More...</a><br/></td></tr>
<tr class="separator:gaf56beeeacad67c0d24ad330ce5c42f90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a4d9b646c26bcf932561699d69d52b1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga0a4d9b646c26bcf932561699d69d52b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a limited self-test on the driver/device.  <a href="#ga0a4d9b646c26bcf932561699d69d52b1">More...</a><br/></td></tr>
<tr class="separator:ga0a4d9b646c26bcf932561699d69d52b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga900a7ab49c2e13b0562ab629c088cf3a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr, u32 NewOptions)</td></tr>
<tr class="memdesc:ga900a7ab49c2e13b0562ab629c088cf3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the options for the IIC device driver.  <a href="#ga900a7ab49c2e13b0562ab629c088cf3a">More...</a><br/></td></tr>
<tr class="separator:ga900a7ab49c2e13b0562ab629c088cf3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf15dd70c4f1bb34a9e35c1ca85cee841"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf15dd70c4f1bb34a9e35c1ca85cee841">XIic_GetOptions</a> (<a class="el" href="struct_x_iic.html">XIic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf15dd70c4f1bb34a9e35c1ca85cee841"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the current options for the IIC device.  <a href="#gaf15dd70c4f1bb34a9e35c1ca85cee841">More...</a><br/></td></tr>
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<tr class="memitem:gaa8c54559d0b1cf0d86c51a0f1d3151eb"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa8c54559d0b1cf0d86c51a0f1d3151eb">XIic_MultiMasterInclude</a> (void)</td></tr>
<tr class="memdesc:gaa8c54559d0b1cf0d86c51a0f1d3151eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function includes multi-master code such that multi-master events are handled properly.  <a href="#gaa8c54559d0b1cf0d86c51a0f1d3151eb">More...</a><br/></td></tr>
<tr class="separator:gaa8c54559d0b1cf0d86c51a0f1d3151eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a848238d75ff57837afa5a58f11f326"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="memdesc:ga7a848238d75ff57837afa5a58f11f326"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive data as a master on the IIC bus.  <a href="#ga7a848238d75ff57837afa5a58f11f326">More...</a><br/></td></tr>
<tr class="separator:ga7a848238d75ff57837afa5a58f11f326"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="memdesc:ga907c577b53407fb0bfc98d0ca37ee221"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send data as a master on the IIC bus.  <a href="#ga907c577b53407fb0bfc98d0ca37ee221">More...</a><br/></td></tr>
<tr class="separator:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)</td></tr>
<tr class="memdesc:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive data as a master on the IIC bus.  <a href="#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">More...</a><br/></td></tr>
<tr class="separator:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeaf11cda2466ae1c6036a3de0f52874"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend</a> (UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option)</td></tr>
<tr class="memdesc:gadeaf11cda2466ae1c6036a3de0f52874"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send data as a master on the IIC bus.  <a href="#gadeaf11cda2466ae1c6036a3de0f52874">More...</a><br/></td></tr>
<tr class="separator:gadeaf11cda2466ae1c6036a3de0f52874"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90f3806cf4817250596f6f68f2c066a3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga90f3806cf4817250596f6f68f2c066a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will wait until the I2C bus is free or timeout.  <a href="#ga90f3806cf4817250596f6f68f2c066a3">More...</a><br/></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:gabf1a99c517996564a1bfa7ccecd1e6f5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_iic___config.html">XIic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabf1a99c517996564a1bfa7ccecd1e6f5">XIic_ConfigTable</a> [XPAR_XIIC_NUM_INSTANCES]</td></tr>
<tr class="memdesc:gabf1a99c517996564a1bfa7ccecd1e6f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IIC configuration table, sized by the number of instances defined in xparameters.h.  <a href="#gabf1a99c517996564a1bfa7ccecd1e6f5">More...</a><br/></td></tr>
<tr class="separator:gabf1a99c517996564a1bfa7ccecd1e6f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1650420711273450b9b406d43f10dd0d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_iic___config.html">XIic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1650420711273450b9b406d43f10dd0d">XIic_ConfigTable</a> []</td></tr>
<tr class="memdesc:ga1650420711273450b9b406d43f10dd0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IIC configuration table, sized by the number of instances defined in xparameters.h.  <a href="#ga1650420711273450b9b406d43f10dd0d">More...</a><br/></td></tr>
<tr class="separator:ga1650420711273450b9b406d43f10dd0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Configuration options</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp50f33d14f129e4548c1c270fd6725a78"></a>The following options may be specified or retrieved for the device and enable/disable additional features of the IIC bus.</p>
<p>Each of the options are bit fields such that more than one may be specified. </p>
</td></tr>
<tr class="memitem:ga44d0ebf5153203223cb5563aaa10a301"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga44d0ebf5153203223cb5563aaa10a301">XII_GENERAL_CALL_OPTION</a>&#160;&#160;&#160;0x00000001</td></tr>
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<tr class="memitem:gaeef2d22ea6248066e075044748f78a0a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeef2d22ea6248066e075044748f78a0a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XII_REPEATED_START_OPTION</b>&#160;&#160;&#160;0x00000002</td></tr>
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<tr class="memitem:gae6c2745bbe258e992bcbe4d0724e4072"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae6c2745bbe258e992bcbe4d0724e4072"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XII_SEND_10_BIT_OPTION</b>&#160;&#160;&#160;0x00000004</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Status events</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpfe694ef0d5388fbe12e4790ff0a37ef4"></a>The following status events occur during IIC bus processing and are passed to the status callback.</p>
<p>Each event is only valid during the appropriate processing of the IIC bus. Each of these events are bit fields such that more than one may be specified. </p>
</td></tr>
<tr class="memitem:ga37e4df461ec4c6ecb22d05e4dfabd841"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga37e4df461ec4c6ecb22d05e4dfabd841">XII_BUS_NOT_BUSY_EVENT</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga37e4df461ec4c6ecb22d05e4dfabd841"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus transitioned to not busy.  <a href="#ga37e4df461ec4c6ecb22d05e4dfabd841">More...</a><br/></td></tr>
<tr class="separator:ga37e4df461ec4c6ecb22d05e4dfabd841"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5843af7de7006ae82767f16bb78ee84e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5843af7de7006ae82767f16bb78ee84e">XII_ARB_LOST_EVENT</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga5843af7de7006ae82767f16bb78ee84e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Arbitration was lost.  <a href="#ga5843af7de7006ae82767f16bb78ee84e">More...</a><br/></td></tr>
<tr class="separator:ga5843af7de7006ae82767f16bb78ee84e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5762b506d3e39139007bb6968cdef80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab5762b506d3e39139007bb6968cdef80">XII_SLAVE_NO_ACK_EVENT</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gab5762b506d3e39139007bb6968cdef80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave did not ACK (had error)  <a href="#gab5762b506d3e39139007bb6968cdef80">More...</a><br/></td></tr>
<tr class="separator:gab5762b506d3e39139007bb6968cdef80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35a6e58757aa1de945b5ed48640e91cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga35a6e58757aa1de945b5ed48640e91cf">XII_MASTER_READ_EVENT</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga35a6e58757aa1de945b5ed48640e91cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master reading from slave.  <a href="#ga35a6e58757aa1de945b5ed48640e91cf">More...</a><br/></td></tr>
<tr class="separator:ga35a6e58757aa1de945b5ed48640e91cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab24f56a64912a6f65c6c87005c9ce892"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab24f56a64912a6f65c6c87005c9ce892">XII_MASTER_WRITE_EVENT</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gab24f56a64912a6f65c6c87005c9ce892"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master writing to slave.  <a href="#gab24f56a64912a6f65c6c87005c9ce892">More...</a><br/></td></tr>
<tr class="separator:gab24f56a64912a6f65c6c87005c9ce892"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0181a51cd40861af2b60cd879f2dd86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab0181a51cd40861af2b60cd879f2dd86">XII_GENERAL_CALL_EVENT</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gab0181a51cd40861af2b60cd879f2dd86"><td class="mdescLeft">&#160;</td><td class="mdescRight">General call to all slaves.  <a href="#gab0181a51cd40861af2b60cd879f2dd86">More...</a><br/></td></tr>
<tr class="separator:gab0181a51cd40861af2b60cd879f2dd86"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp092729737d14686054aa21531a3582c6"></a>Register offsets for the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> device. </p>
</td></tr>
<tr class="memitem:gaa27d0e422717f97fac36688f403d320a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:gaa27d0e422717f97fac36688f403d320a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable Register.  <a href="#gaa27d0e422717f97fac36688f403d320a">More...</a><br/></td></tr>
<tr class="separator:gaa27d0e422717f97fac36688f403d320a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe67d115440977750c9a7299eb499798"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gafe67d115440977750c9a7299eb499798"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="#gafe67d115440977750c9a7299eb499798">More...</a><br/></td></tr>
<tr class="separator:gafe67d115440977750c9a7299eb499798"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a6353babc7347287755655c810a1758"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:ga6a6353babc7347287755655c810a1758"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="#ga6a6353babc7347287755655c810a1758">More...</a><br/></td></tr>
<tr class="separator:ga6a6353babc7347287755655c810a1758"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2129f15b6d659403e4aa18355aa67884"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2129f15b6d659403e4aa18355aa67884">XIIC_RESETR_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:ga2129f15b6d659403e4aa18355aa67884"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset Register.  <a href="#ga2129f15b6d659403e4aa18355aa67884">More...</a><br/></td></tr>
<tr class="separator:ga2129f15b6d659403e4aa18355aa67884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="memdesc:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="#ga03585e458e3c5adf56986e7c2c3d9d42">More...</a><br/></td></tr>
<tr class="separator:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa039f3dea3b57add15de333f733b5561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>&#160;&#160;&#160;0x104</td></tr>
<tr class="memdesc:gaa039f3dea3b57add15de333f733b5561"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="#gaa039f3dea3b57add15de333f733b5561">More...</a><br/></td></tr>
<tr class="separator:gaa039f3dea3b57add15de333f733b5561"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>&#160;&#160;&#160;0x108</td></tr>
<tr class="memdesc:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Tx Register.  <a href="#ga63ef537f0fba0aa0c68f9be05516c6c9">More...</a><br/></td></tr>
<tr class="separator:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8b1aea0734d4d8fc3d883ef2d6d63494">XIIC_DRR_REG_OFFSET</a>&#160;&#160;&#160;0x10C</td></tr>
<tr class="memdesc:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Rx Register.  <a href="#ga8b1aea0734d4d8fc3d883ef2d6d63494">More...</a><br/></td></tr>
<tr class="separator:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga831a9fbdcfebad501e336231321be40a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga831a9fbdcfebad501e336231321be40a">XIIC_ADR_REG_OFFSET</a>&#160;&#160;&#160;0x110</td></tr>
<tr class="memdesc:ga831a9fbdcfebad501e336231321be40a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Register.  <a href="#ga831a9fbdcfebad501e336231321be40a">More...</a><br/></td></tr>
<tr class="separator:ga831a9fbdcfebad501e336231321be40a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3b1a6b1edb70a36a0d44ccf0d39a885f">XIIC_TFO_REG_OFFSET</a>&#160;&#160;&#160;0x114</td></tr>
<tr class="memdesc:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Occupancy.  <a href="#ga3b1a6b1edb70a36a0d44ccf0d39a885f">More...</a><br/></td></tr>
<tr class="separator:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe647af8022928553f2fd3bb05bfa80a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabe647af8022928553f2fd3bb05bfa80a">XIIC_RFO_REG_OFFSET</a>&#160;&#160;&#160;0x118</td></tr>
<tr class="memdesc:gabe647af8022928553f2fd3bb05bfa80a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Occupancy.  <a href="#gabe647af8022928553f2fd3bb05bfa80a">More...</a><br/></td></tr>
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<tr class="memitem:gaf50b1672278bdf573cd74e36768b0cda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf50b1672278bdf573cd74e36768b0cda">XIIC_TBA_REG_OFFSET</a>&#160;&#160;&#160;0x11C</td></tr>
<tr class="memdesc:gaf50b1672278bdf573cd74e36768b0cda"><td class="mdescLeft">&#160;</td><td class="mdescRight">10 Bit Address reg  <a href="#gaf50b1672278bdf573cd74e36768b0cda">More...</a><br/></td></tr>
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<tr class="memitem:gad032470e4ff2a3760aa63f2c3d7e5240"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:gad032470e4ff2a3760aa63f2c3d7e5240"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Depth reg.  <a href="#gad032470e4ff2a3760aa63f2c3d7e5240">More...</a><br/></td></tr>
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<tr class="memitem:gaf901951024f3144cd51ce84d897a5f5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf901951024f3144cd51ce84d897a5f5b">XIIC_GPO_REG_OFFSET</a>&#160;&#160;&#160;0x124</td></tr>
<tr class="memdesc:gaf901951024f3144cd51ce84d897a5f5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Register.  <a href="#gaf901951024f3144cd51ce84d897a5f5b">More...</a><br/></td></tr>
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Device Global Interrupt Enable Register masks (CR) mask(s)</h2></td></tr>
<tr class="memitem:gaec62fb2c2f3894266187fa408c256891"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">XIIC_GINTR_ENABLE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gaec62fb2c2f3894266187fa408c256891"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable Mask.  <a href="#gaec62fb2c2f3894266187fa408c256891">More...</a><br/></td></tr>
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IIC Device Interrupt Status/Enable (INTR) Register Masks</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpb60ed021a8c45827ed41c3c0bddebdd1"></a><b> Interrupt Status Register (IISR) </b></p>
<p>This register holds the interrupt status flags for the Spi device.</p>
<p><b> Interrupt Enable Register (IIER) </b></p>
<p>This register is used to enable interrupt sources for the IIC device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>IISR/IIER registers have the same bit definitions and are only defined once. </p>
</td></tr>
<tr class="memitem:gabb6a638c0aa6ee9e3b50dc5d2ca56770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gabb6a638c0aa6ee9e3b50dc5d2ca56770"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Arbitration lost  <a href="#gabb6a638c0aa6ee9e3b50dc5d2ca56770">More...</a><br/></td></tr>
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<tr class="memitem:gaa1ea99d449fd02f69d41d0f41f093282"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa1ea99d449fd02f69d41d0f41f093282"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx error/msg complete  <a href="#gaa1ea99d449fd02f69d41d0f41f093282">More...</a><br/></td></tr>
<tr class="separator:gaa1ea99d449fd02f69d41d0f41f093282"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc15e89e891805d58f729c4d1f56b093"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gadc15e89e891805d58f729c4d1f56b093"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO/reg empty  <a href="#gadc15e89e891805d58f729c4d1f56b093">More...</a><br/></td></tr>
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<tr class="memitem:gac96fa03c6a514cd87cb9deadaef7e574"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gac96fa03c6a514cd87cb9deadaef7e574"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO/reg=OCY level  <a href="#gac96fa03c6a514cd87cb9deadaef7e574">More...</a><br/></td></tr>
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<tr class="memitem:ga52e6f9aadc4cc828509347c6768d2c25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga52e6f9aadc4cc828509347c6768d2c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Bus not busy  <a href="#ga52e6f9aadc4cc828509347c6768d2c25">More...</a><br/></td></tr>
<tr class="separator:ga52e6f9aadc4cc828509347c6768d2c25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88cf05913ad5693c477993c2af6cbd7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga88cf05913ad5693c477993c2af6cbd7e">XIIC_INTR_AAS_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga88cf05913ad5693c477993c2af6cbd7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = When addr as slave  <a href="#ga88cf05913ad5693c477993c2af6cbd7e">More...</a><br/></td></tr>
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<tr class="memitem:gab153bb7f21133bf7471c70f4089494a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab153bb7f21133bf7471c70f4089494a5">XIIC_INTR_NAAS_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gab153bb7f21133bf7471c70f4089494a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Not addr as slave  <a href="#gab153bb7f21133bf7471c70f4089494a5">More...</a><br/></td></tr>
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<tr class="memitem:ga4af241dbcd0cb4184fe594d09954f69c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga4af241dbcd0cb4184fe594d09954f69c"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO half empty  <a href="#ga4af241dbcd0cb4184fe594d09954f69c">More...</a><br/></td></tr>
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<tr class="memitem:gac9441942c102ac8a8485609d98ba5d5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac9441942c102ac8a8485609d98ba5d5c">XIIC_TX_INTERRUPTS</a></td></tr>
<tr class="memdesc:gac9441942c102ac8a8485609d98ba5d5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">All Tx interrupts commonly used.  <a href="#gac9441942c102ac8a8485609d98ba5d5c">More...</a><br/></td></tr>
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<tr class="memitem:gac942198f619f45e2705457967e1683c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac942198f619f45e2705457967e1683c8">XIIC_TX_RX_INTERRUPTS</a>&#160;&#160;&#160;(<a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a> | <a class="el" href="group___overview.html#gac9441942c102ac8a8485609d98ba5d5c">XIIC_TX_INTERRUPTS</a>)</td></tr>
<tr class="memdesc:gac942198f619f45e2705457967e1683c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts commonly used.  <a href="#gac942198f619f45e2705457967e1683c8">More...</a><br/></td></tr>
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Reset Register mask</h2></td></tr>
<tr class="memitem:gad29589acad66518bac5f21a670ccc9a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad29589acad66518bac5f21a670ccc9a5">XIIC_RESET_MASK</a>&#160;&#160;&#160;0x0000000A</td></tr>
<tr class="memdesc:gad29589acad66518bac5f21a670ccc9a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RESET Mask.  <a href="#gad29589acad66518bac5f21a670ccc9a5">More...</a><br/></td></tr>
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Control Register masks (CR) mask(s)</h2></td></tr>
<tr class="memitem:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa4fa9698cb076131f2d4571ef3bae6f3">XIIC_CR_ENABLE_DEVICE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device enable = 1.  <a href="#gaa4fa9698cb076131f2d4571ef3bae6f3">More...</a><br/></td></tr>
<tr class="separator:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2342662b2911c5aea24b397e17be7e41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2342662b2911c5aea24b397e17be7e41">XIIC_CR_TX_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga2342662b2911c5aea24b397e17be7e41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO reset=1.  <a href="#ga2342662b2911c5aea24b397e17be7e41">More...</a><br/></td></tr>
<tr class="separator:ga2342662b2911c5aea24b397e17be7e41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa18a79f31c286ce3daf88d677096d9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gafa18a79f31c286ce3daf88d677096d9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master starts Txing=1.  <a href="#gafa18a79f31c286ce3daf88d677096d9d">More...</a><br/></td></tr>
<tr class="separator:gafa18a79f31c286ce3daf88d677096d9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dir of Tx.  <a href="#gaefca9cb59ce820ea4fbb4c35f5a1fa55">More...</a><br/></td></tr>
<tr class="separator:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79990adaa6f077302644d7b787b19c53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga79990adaa6f077302644d7b787b19c53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Ack.  <a href="#ga79990adaa6f077302644d7b787b19c53">More...</a><br/></td></tr>
<tr class="separator:ga79990adaa6f077302644d7b787b19c53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="mdescLeft">&#160;</td><td class="mdescRight">Repeated start = 1.  <a href="#ga5d0c5d60de4fd0ca22e12b8be3870656">More...</a><br/></td></tr>
<tr class="separator:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9dda6b07f8f4d2962b8833b05b8603b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac9dda6b07f8f4d2962b8833b05b8603b">XIIC_CR_GENERAL_CALL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gac9dda6b07f8f4d2962b8833b05b8603b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gen Call enabled = 1.  <a href="#gac9dda6b07f8f4d2962b8833b05b8603b">More...</a><br/></td></tr>
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Status Register masks (SR) mask(s)</h2></td></tr>
<tr class="memitem:gaac5399a034245e8adaa09f301bc4968c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaac5399a034245e8adaa09f301bc4968c">XIIC_SR_GEN_CALL_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaac5399a034245e8adaa09f301bc4968c"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = A Master issued a GC  <a href="#gaac5399a034245e8adaa09f301bc4968c">More...</a><br/></td></tr>
<tr class="separator:gaac5399a034245e8adaa09f301bc4968c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = When addressed as slave  <a href="#gab0fe4841630cc66a6b93e5a5d2512fde">More...</a><br/></td></tr>
<tr class="separator:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Bus is busy  <a href="#ga41bc9ddb46bd9eca389b60503e7a0589">More...</a><br/></td></tr>
<tr class="separator:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98dda884f247690398dfd64b358c8769"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga98dda884f247690398dfd64b358c8769">XIIC_SR_MSTR_RDING_SLAVE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga98dda884f247690398dfd64b358c8769"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Dir: Master &lt;&ndash; slave  <a href="#ga98dda884f247690398dfd64b358c8769">More...</a><br/></td></tr>
<tr class="separator:ga98dda884f247690398dfd64b358c8769"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9ccf53df4527f615d7b6b640a5e7a5e8">XIIC_SR_TX_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO full  <a href="#ga9ccf53df4527f615d7b6b640a5e7a5e8">More...</a><br/></td></tr>
<tr class="separator:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadccbbf3c41f7d44b6e1a85d72157ed08">XIIC_SR_RX_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO full  <a href="#gadccbbf3c41f7d44b6e1a85d72157ed08">More...</a><br/></td></tr>
<tr class="separator:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee53acd662dfc1cca568f88401620780"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaee53acd662dfc1cca568f88401620780">XIIC_SR_RX_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaee53acd662dfc1cca568f88401620780"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO empty  <a href="#gaee53acd662dfc1cca568f88401620780">More...</a><br/></td></tr>
<tr class="separator:gaee53acd662dfc1cca568f88401620780"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e6ab2b0daa0a08862d649fb769f87e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3e6ab2b0daa0a08862d649fb769f87e9">XIIC_SR_TX_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga3e6ab2b0daa0a08862d649fb769f87e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO empty  <a href="#ga3e6ab2b0daa0a08862d649fb769f87e9">More...</a><br/></td></tr>
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Data Tx Register (DTR) mask(s)</h2></td></tr>
<tr class="memitem:ga958c3a8926423eed1b2c16aa56938257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga958c3a8926423eed1b2c16aa56938257"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Set dynamic start  <a href="#ga958c3a8926423eed1b2c16aa56938257">More...</a><br/></td></tr>
<tr class="separator:ga958c3a8926423eed1b2c16aa56938257"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Set dynamic stop  <a href="#ga7efb5db8358e4ce8fa761d0227f52fba">More...</a><br/></td></tr>
<tr class="separator:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f43797e583841a89bfc81c9d2b8bd1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9f43797e583841a89bfc81c9d2b8bd1b">IIC_TX_FIFO_DEPTH</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga9f43797e583841a89bfc81c9d2b8bd1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx fifo capacity.  <a href="#ga9f43797e583841a89bfc81c9d2b8bd1b">More...</a><br/></td></tr>
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Data Rx Register (DRR) mask(s)</h2></td></tr>
<tr class="memitem:ga23db93d1ef8c4651eba08f22fff2ee36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga23db93d1ef8c4651eba08f22fff2ee36">IIC_RX_FIFO_DEPTH</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga23db93d1ef8c4651eba08f22fff2ee36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx fifo capacity.  <a href="#ga23db93d1ef8c4651eba08f22fff2ee36">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga23db93d1ef8c4651eba08f22fff2ee36"></a>
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          <td class="memname">#define IIC_RX_FIFO_DEPTH&#160;&#160;&#160;16</td>
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<p>Rx fifo capacity. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, and <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>.</p>

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<p>Tx fifo capacity. </p>

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          <td class="memname">#define XII_ADDR_TO_RESPOND_TYPE&#160;&#160;&#160;2</td>
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<p>This device's bus address as slave. </p>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, <a class="el" href="group___overview.html#ga3e8f77e5df8d92a4b27627e03b5e1807">XIic_GetAddress()</a>, and <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress()</a>.</p>

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          <td class="memname">#define XII_ADDR_TO_SEND_TYPE&#160;&#160;&#160;1</td>
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<p>Bus address of slave device. </p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>, and <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress()</a>.</p>

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          <td class="memname">#define XII_ARB_LOST_EVENT&#160;&#160;&#160;0x00000002</td>
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<p>Arbitration was lost. </p>

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          <td class="memname">#define XII_BUS_NOT_BUSY_EVENT&#160;&#160;&#160;0x00000001</td>
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<p>Bus transitioned to not busy. </p>

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          <td class="memname">#define XII_GENERAL_CALL_EVENT&#160;&#160;&#160;0x00000020</td>
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<p>General call to all slaves. </p>

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<pre>
XII_GENERAL_CALL_OPTION The general call option allows an IIC slave to
                        recognized the general call address. The status
                        handler is called as usual indicating the device
                        has been addressed as a slave with a general
                        call. It is the application's responsibility to
                        perform any special processing for the general
                        call.</pre><pre>XII_REPEATED_START_OPTION       The repeated start option allows multiple
                        messages to be sent/received on the IIC bus
                        without rearbitrating for the bus.  The messages
                        are sent as a series of messages such that the
                        option must be enabled before the 1st message of
                        the series, to prevent an stop condition from
                        being generated on the bus, and disabled before
                        the last message of the series, to allow the
                        stop condition to be generated.</pre><pre>XII_SEND_10_BIT_OPTION  The send 10 bit option allows 10 bit addresses
                        to be sent on the bus when the device is a
                        master. The device can be configured to respond
                        as to 7 bit addresses even though it may be
                        communicating with other devices that support 10
                        bit addresses.  When this option is not enabled,
                        only 7 bit addresses are sent on the bus.</pre><pre></pre> 
<p>Referenced by <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>.</p>

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          <td class="memname">#define XII_MASTER_READ_EVENT&#160;&#160;&#160;0x00000008</td>
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<p>Master reading from slave. </p>

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          <td class="memname">#define XII_MASTER_WRITE_EVENT&#160;&#160;&#160;0x00000010</td>
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<p>Master writing to slave. </p>

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          <td class="memname">#define XII_SLAVE_NO_ACK_EVENT&#160;&#160;&#160;0x00000004</td>
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<p>Slave did not ACK (had error) </p>

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          <td class="memname">#define XIIC_ADR_REG_OFFSET&#160;&#160;&#160;0x110</td>
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<p>Address Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga3e8f77e5df8d92a4b27627e03b5e1807">XIic_GetAddress()</a>, and <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress()</a>.</p>

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          <td class="memname">#define XIic_ClearIisr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InterruptMask&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a>((BaseAddress),                   \</div>
<div class="line">        <a class="code" href="group___overview.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a>(BaseAddress) &amp; (InterruptMask))</div>
<div class="ttc" id="group___overview_html_gaf69a6487ad62b105aa3bb8d0e25b7fe7"><div class="ttname"><a href="group___overview.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a></div><div class="ttdeci">#define XIic_ReadIisr(BaseAddress)</div><div class="ttdoc">This function gets the contents of the Interrupt Status Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:384</div></div>
<div class="ttc" id="group___overview_html_ga3bc448908013aceb690c84fdbb7d66a8"><div class="ttname"><a href="group___overview.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a></div><div class="ttdeci">#define XIic_WriteIisr(BaseAddress, Status)</div><div class="ttdoc">This function sets the Interrupt status register to the specified value. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:365</div></div>
</div><!-- fragment -->
<p>This macro clears the specified interrupt in the Interrupt status register. </p>
<p>It is non-destructive in that the register is read and only the interrupt specified is cleared. Clearing an interrupt acknowledges it.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device. </td></tr>
    <tr><td class="paramname">InterruptMask</td><td>is the bit mask of the interrupts to be cleared.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55" title="This macro clears the specified interrupt in the Interrupt status register. ">XIic_ClearIisr(u32 BaseAddress, u32 InterruptMask)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIIC_CR_DIR_IS_TX_MASK&#160;&#160;&#160;0x00000008</td>
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<p>Dir of Tx. </p>
<p>Txing=1 </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIIC_CR_ENABLE_DEVICE_MASK&#160;&#160;&#160;0x00000001</td>
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<p>Device enable = 1. </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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<p>Gen Call enabled = 1. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>.</p>

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<p>Master starts Txing=1. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIIC_CR_NO_ACK_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tx Ack. </p>
<p>NO ack = 1 </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, and <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>.</p>

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          <td class="memname">#define XIIC_CR_REG_OFFSET&#160;&#160;&#160;0x100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control Register. </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>, <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>, <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIIC_CR_REPEATED_START_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeated start = 1. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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<a class="anchor" id="ga2342662b2911c5aea24b397e17be7e41"></a>
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          <td class="memname">#define XIIC_CR_TX_FIFO_RESET_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
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<p>Transmit FIFO reset=1. </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, and <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>.</p>

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<a class="anchor" id="gaa27d0e422717f97fac36688f403d320a"></a>
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          <td class="memname">#define XIIC_DGIER_OFFSET&#160;&#160;&#160;0x1C</td>
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      </table>
</div><div class="memdoc">

<p>Global Interrupt Enable Register. </p>

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          <td class="memname">#define XIIC_DRR_REG_OFFSET&#160;&#160;&#160;0x10C</td>
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<p>Data Rx Register. </p>

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<a class="anchor" id="ga63ef537f0fba0aa0c68f9be05516c6c9"></a>
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          <td class="memname">#define XIIC_DTR_REG_OFFSET&#160;&#160;&#160;0x108</td>
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      </table>
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<p>Data Tx Register. </p>

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<a class="anchor" id="ga81d32f9fd29736e9f9c7ef345527386b"></a>
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          <td class="memname">#define XIic_DynSend7BitAddress</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SlaveAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Operation&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{                                                                       \</div>
<div class="line">        u8 LocalAddr = (u8)(SlaveAddress &lt;&lt; 1);                         \</div>
<div class="line">        LocalAddr = (LocalAddr &amp; 0xFE) | (Operation);                   <a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">	XIic_WriteReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>,                \</div>
<div class="line">                        <a class="code" href="group___overview.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a> | LocalAddr);            \</div>
<div class="line">}</div>
<div class="ttc" id="group___overview_html_ga63ef537f0fba0aa0c68f9be05516c6c9"><div class="ttname"><a href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a></div><div class="ttdeci">#define XIIC_DTR_REG_OFFSET</div><div class="ttdoc">Data Tx Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:90</div></div>
<div class="ttc" id="group___overview_html_ga958c3a8926423eed1b2c16aa56938257"><div class="ttname"><a href="group___overview.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a></div><div class="ttdeci">#define XIIC_TX_DYN_START_MASK</div><div class="ttdoc">1 = Set dynamic start </div><div class="ttdef"><b>Definition:</b> xiic_l.h:191</div></div>
<div class="ttc" id="group___overview_html_ga7a9318f43afc81c1dbd30a27587ba51d"><div class="ttname"><a href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a></div><div class="ttdeci">#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write to the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:281</div></div>
</div><!-- fragment -->
<p>This macro sends the address for a 7 bit address during both read and write operations. </p>
<p>It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers for Dynamic controller functionality.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">SlaveAddress</td><td>is the address of the slave to send to. </td></tr>
    <tr><td class="paramname">Operation</td><td>indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XIic_DynSend7BitAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation); </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, and <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>.</p>

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<a class="anchor" id="ga682d21ed5020daa5b5a863bbffb35cc5"></a>
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          <td class="memname">#define XIic_DynSendStartStopAddress</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SlaveAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Operation&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{                                                                        \</div>
<div class="line">        u8 LocalAddr = (u8)(SlaveAddress &lt;&lt; 1);                          \</div>
<div class="line">        LocalAddr = (LocalAddr &amp; 0xFE) | (Operation);                    <a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">	XIic_WriteReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>,                 \</div>
<div class="line">                        <a class="code" href="group___overview.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a> | <a class="code" href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a> | \</div>
<div class="line">                        LocalAddr);                                      \</div>
<div class="line">}</div>
<div class="ttc" id="group___overview_html_ga63ef537f0fba0aa0c68f9be05516c6c9"><div class="ttname"><a href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a></div><div class="ttdeci">#define XIIC_DTR_REG_OFFSET</div><div class="ttdoc">Data Tx Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:90</div></div>
<div class="ttc" id="group___overview_html_ga958c3a8926423eed1b2c16aa56938257"><div class="ttname"><a href="group___overview.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a></div><div class="ttdeci">#define XIIC_TX_DYN_START_MASK</div><div class="ttdoc">1 = Set dynamic start </div><div class="ttdef"><b>Definition:</b> xiic_l.h:191</div></div>
<div class="ttc" id="group___overview_html_ga7a9318f43afc81c1dbd30a27587ba51d"><div class="ttname"><a href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a></div><div class="ttdeci">#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write to the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:281</div></div>
<div class="ttc" id="group___overview_html_ga7efb5db8358e4ce8fa761d0227f52fba"><div class="ttname"><a href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a></div><div class="ttdeci">#define XIIC_TX_DYN_STOP_MASK</div><div class="ttdoc">1 = Set dynamic stop </div><div class="ttdef"><b>Definition:</b> xiic_l.h:192</div></div>
</div><!-- fragment -->
<p>This macro sends the address, start and stop for a 7 bit address during both write operations. </p>
<p>It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">SlaveAddress</td><td>is the address of the slave to send to. </td></tr>
    <tr><td class="paramname">Operation</td><td>indicates XIIC_WRITE_OPERATION.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XIic_DynSendStartStopAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation); </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>.</p>

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<a class="anchor" id="ga22446f72b705b950e4b485ab9cdd2ae6"></a>
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          <td class="memname">#define XIic_DynSendStop</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">ByteCount&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{                                                                       <a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">	XIic_WriteReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>,                \</div>
<div class="line">                        <a class="code" href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a> | ByteCount);             \</div>
<div class="line">}</div>
<div class="ttc" id="group___overview_html_ga63ef537f0fba0aa0c68f9be05516c6c9"><div class="ttname"><a href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a></div><div class="ttdeci">#define XIIC_DTR_REG_OFFSET</div><div class="ttdoc">Data Tx Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:90</div></div>
<div class="ttc" id="group___overview_html_ga7a9318f43afc81c1dbd30a27587ba51d"><div class="ttname"><a href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a></div><div class="ttdeci">#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write to the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:281</div></div>
<div class="ttc" id="group___overview_html_ga7efb5db8358e4ce8fa761d0227f52fba"><div class="ttname"><a href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a></div><div class="ttdeci">#define XIIC_TX_DYN_STOP_MASK</div><div class="ttdoc">1 = Set dynamic stop </div><div class="ttdef"><b>Definition:</b> xiic_l.h:192</div></div>
</div><!-- fragment -->
<p>This macro sends a stop condition on IIC bus for Dynamic logic. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of Rx bytes received before the master. doesn't respond with ACK.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga22446f72b705b950e4b485ab9cdd2ae6" title="This macro sends a stop condition on IIC bus for Dynamic logic. ">XIic_DynSendStop(u32 BaseAddress, u32 ByteCount)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, and <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>.</p>

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<a class="anchor" id="gaec62fb2c2f3894266187fa408c256891"></a>
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          <td class="memname">#define XIIC_GINTR_ENABLE_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Global Interrupt Enable Mask. </p>

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<a class="anchor" id="gaf901951024f3144cd51ce84d897a5f5b"></a>
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<div class="memproto">
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          <td class="memname">#define XIIC_GPO_REG_OFFSET&#160;&#160;&#160;0x124</td>
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      </table>
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<p>Output Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4108f79d22b71e2455844a8487b1a776">XIic_GetGpOutput()</a>, and <a class="el" href="group___overview.html#gafe4e886e72abb9d860a6cb83c84c74a1">XIic_SetGpOutput()</a>.</p>

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<a class="anchor" id="ga6a6353babc7347287755655c810a1758"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XIIC_IIER_OFFSET&#160;&#160;&#160;0x28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Enable Register. </p>

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<a class="anchor" id="gafe67d115440977750c9a7299eb499798"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XIIC_IISR_OFFSET&#160;&#160;&#160;0x20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Status Register. </p>

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<a class="anchor" id="ga88cf05913ad5693c477993c2af6cbd7e"></a>
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          <td class="memname">#define XIIC_INTR_AAS_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>1 = When addr as slave </p>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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<a class="anchor" id="gabb6a638c0aa6ee9e3b50dc5d2ca56770"></a>
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          <td class="memname">#define XIIC_INTR_ARB_LOST_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>1 = Arbitration lost </p>

<p>Referenced by <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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<a class="anchor" id="ga52e6f9aadc4cc828509347c6768d2c25"></a>
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          <td class="memname">#define XIIC_INTR_BNB_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
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<p>1 = Bus not busy </p>

<p>Referenced by <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIIC_INTR_NAAS_MASK&#160;&#160;&#160;0x00000040</td>
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<p>1 = Not addr as slave </p>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>.</p>

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          <td class="memname">#define XIIC_INTR_RX_FULL_MASK&#160;&#160;&#160;0x00000008</td>
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<p>1 = Rx FIFO/reg=OCY level </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>.</p>

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          <td class="memname">#define XIIC_INTR_TX_EMPTY_MASK&#160;&#160;&#160;0x00000004</td>
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<p>1 = Tx FIFO/reg empty </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, and <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>.</p>

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          <td class="memname">#define XIIC_INTR_TX_ERROR_MASK&#160;&#160;&#160;0x00000002</td>
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<p>1 = Tx error/msg complete </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, and <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>.</p>

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<p>1 = Tx FIFO half empty </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, and <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>.</p>

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          <td class="memname">#define XIic_IntrGlobalDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td>&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>, 0)</td>
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<p>This macro disables all interrupts for the device by writing to the Global interrupt enable register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e" title="This macro disables all interrupts for the device by writing to the Global interrupt enable register...">XIic_IntrGlobalDisable(u32 BaseAddress)</a>; </dd></dl>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a91e062862cf2b2bf6c6f8120baa882be">SlaveReadData()</a>, <a class="el" href="xiic__slave__example_8c.html#a0f41d940d34ed71035e6f6aeb24bdf67">SlaveWriteData()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#adc9d7e63c6a7961710a9ae7df6b824d7">TenBitAddrReadData()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#a2e451cd59da6f2b702a42a4fcb21a362">TenBitAddrWriteData()</a>, <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIic_IntrGlobalEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>,                 \</div>
<div class="line">                <a class="code" href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">XIIC_GINTR_ENABLE_MASK</a>)</div>
<div class="ttc" id="group___overview_html_gaa27d0e422717f97fac36688f403d320a"><div class="ttname"><a href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a></div><div class="ttdeci">#define XIIC_DGIER_OFFSET</div><div class="ttdoc">Global Interrupt Enable Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:84</div></div>
<div class="ttc" id="group___overview_html_ga7a9318f43afc81c1dbd30a27587ba51d"><div class="ttname"><a href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a></div><div class="ttdeci">#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write to the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:281</div></div>
<div class="ttc" id="group___overview_html_gaec62fb2c2f3894266187fa408c256891"><div class="ttname"><a href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">XIIC_GINTR_ENABLE_MASK</a></div><div class="ttdeci">#define XIIC_GINTR_ENABLE_MASK</div><div class="ttdoc">Global Interrupt Enable Mask. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:105</div></div>
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<p>This macro writes to the global interrupt enable register to enable interrupts from the device. </p>
<p>This function does not enable individual interrupts as the Interrupt Enable Register must be set appropriately.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21" title="This macro writes to the global interrupt enable register to enable interrupts from the device...">XIic_IntrGlobalEnable(u32 BaseAddress)</a>; </dd></dl>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a91e062862cf2b2bf6c6f8120baa882be">SlaveReadData()</a>, <a class="el" href="xiic__slave__example_8c.html#a0f41d940d34ed71035e6f6aeb24bdf67">SlaveWriteData()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#adc9d7e63c6a7961710a9ae7df6b824d7">TenBitAddrReadData()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#a2e451cd59da6f2b702a42a4fcb21a362">TenBitAddrWriteData()</a>, <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>, <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>, <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIic_IsIntrGlobalEnabled</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td></td>
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<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="code" href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>) ==              <a class="code" href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">\</a></div>
<div class="line"><a class="code" href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">		XIIC_GINTR_ENABLE_MASK</a>)</div>
<div class="ttc" id="group___overview_html_gaa27d0e422717f97fac36688f403d320a"><div class="ttname"><a href="group___overview.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a></div><div class="ttdeci">#define XIIC_DGIER_OFFSET</div><div class="ttdoc">Global Interrupt Enable Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:84</div></div>
<div class="ttc" id="group___overview_html_gab28be58b11c65ecc54fc2f0c300412c1"><div class="ttname"><a href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a></div><div class="ttdeci">#define XIic_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read from the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:258</div></div>
<div class="ttc" id="group___overview_html_gaec62fb2c2f3894266187fa408c256891"><div class="ttname"><a href="group___overview.html#gaec62fb2c2f3894266187fa408c256891">XIIC_GINTR_ENABLE_MASK</a></div><div class="ttdeci">#define XIIC_GINTR_ENABLE_MASK</div><div class="ttdoc">Global Interrupt Enable Mask. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:105</div></div>
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<p>This function determines if interrupts are enabled at the global level by reading the global interrupt register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if the global interrupt is enabled.</li>
<li>FALSE if global interrupt is disabled.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: int <a class="el" href="group___overview.html#gaa839067df3b55f3181db24ebd8db3187" title="This function determines if interrupts are enabled at the global level by reading the global interrup...">XIic_IsIntrGlobalEnabled(u32 BaseAddress)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, and <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>.</p>

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<p>The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave. </p>
<p>Master on the IIC bus </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, and <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>.</p>

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          <td class="memname">#define XIIC_READ_OPERATION&#160;&#160;&#160;1</td>
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<p>The following constants are used to specify whether to do Read or a Write operation on IIC bus. </p>
<p>Read operation on the IIC bus </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, and <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>.</p>

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          <td class="memname">#define XIic_ReadIier</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td>&#160;&#160;&#160;<a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>)</td>
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<p>This function gets the Interrupt Enable Register contents. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The contents read from the Interrupt Enable Register. Bit positions of 1 indicate that the corresponding interrupt is enabled. Bit positions of 0 indicate that the corresponding interrupt is disabled.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 <a class="el" href="group___overview.html#gaee17ffc86a8270abeb1319e8c67ccce5" title="This function gets the Interrupt Enable Register contents. ">XIic_ReadIier(u32 BaseAddress)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, and <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>.</p>

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          <td class="memname">#define XIic_ReadIisr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td>&#160;&#160;&#160;<a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>)</td>
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<p>This function gets the contents of the Interrupt Status Register. </p>
<p>This register indicates the status of interrupt sources for the device. The status is independent of whether interrupts are enabled such that the status register may also be polled when interrupts are not enabled.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value read from the Interrupt Status Register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 <a class="el" href="group___overview.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7" title="This function gets the contents of the Interrupt Status Register. ">XIic_ReadIisr(u32 BaseAddress)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>.</p>

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          <td class="memname">#define XIic_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XIic_In32((BaseAddress) + (RegOffset))</td>
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<p>Read from the specified IIC device register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset from the 1st register of the device to select the specific register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value read from the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1" title="Read from the specified IIC device register. ">XIic_ReadReg(u32 BaseAddress, u32 RegOffset)</a>; <pre class="fragment">    This macro does not do any checking to ensure that the
</pre> register exists if the register may be excluded due to parameterization, such as the GPO Register. </dd></dl>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>, <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga3e8f77e5df8d92a4b27627e03b5e1807">XIic_GetAddress()</a>, <a class="el" href="group___overview.html#ga4108f79d22b71e2455844a8487b1a776">XIic_GetGpOutput()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#gaa4b84f9d58cbd40d2633140d79e2aed4">XIic_IsSlave()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIIC_REPEATED_START&#160;&#160;&#160;0x01</td>
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<p>Donot Send a stop on the IIC bus after the current data transfer. </p>

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          <td class="memname">#define XIIC_RESET_MASK&#160;&#160;&#160;0x0000000A</td>
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<p>RESET Mask. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset()</a>.</p>

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          <td class="memname">#define XIIC_RESETR_OFFSET&#160;&#160;&#160;0x40</td>
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<p>Reset Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset()</a>.</p>

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          <td class="memname">#define XIIC_RFD_REG_OFFSET&#160;&#160;&#160;0x120</td>
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<p>Rx FIFO Depth reg. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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          <td class="memname">#define XIIC_RFO_REG_OFFSET&#160;&#160;&#160;0x118</td>
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<p>Rx FIFO Occupancy. </p>

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          <td class="memname">#define XIic_Send7BitAddress</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SlaveAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Operation&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">{                                                                       \</div>
<div class="line">        u8 LocalAddr = (u8)(SlaveAddress &lt;&lt; 1);                         \</div>
<div class="line">        LocalAddr = (LocalAddr &amp; 0xFE) | (Operation);                   <a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">	XIic_WriteReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>, LocalAddr);    \</div>
<div class="line">}</div>
<div class="ttc" id="group___overview_html_ga63ef537f0fba0aa0c68f9be05516c6c9"><div class="ttname"><a href="group___overview.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a></div><div class="ttdeci">#define XIIC_DTR_REG_OFFSET</div><div class="ttdoc">Data Tx Register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:90</div></div>
<div class="ttc" id="group___overview_html_ga7a9318f43afc81c1dbd30a27587ba51d"><div class="ttname"><a href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a></div><div class="ttdeci">#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write to the specified IIC device register. </div><div class="ttdef"><b>Definition:</b> xiic_l.h:281</div></div>
</div><!-- fragment -->
<p>This macro sends the address for a 7 bit address during both read and write operations. </p>
<p>It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">SlaveAddress</td><td>is the address of the slave to send to. </td></tr>
    <tr><td class="paramname">Operation</td><td>indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XIic_Send7BitAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation); </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIIC_SLAVE_ROLE&#160;&#160;&#160;0</td>
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<p>Slave on the IIC bus. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>.</p>

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          <td class="memname">#define XIIC_SR_ADDR_AS_SLAVE_MASK&#160;&#160;&#160;0x00000002</td>
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<p>1 = When addressed as slave </p>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#gaa4b84f9d58cbd40d2633140d79e2aed4">XIic_IsSlave()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIIC_SR_BUS_BUSY_MASK&#160;&#160;&#160;0x00000004</td>
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<p>1 = Bus is busy </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIIC_SR_GEN_CALL_MASK&#160;&#160;&#160;0x00000001</td>
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<p>1 = A Master issued a GC </p>

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<p>1 = Dir: Master &lt;&ndash; slave </p>

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          <td class="memname">#define XIIC_SR_REG_OFFSET&#160;&#160;&#160;0x104</td>
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<p>Status Register. </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>, <a class="el" href="group___overview.html#gaa4b84f9d58cbd40d2633140d79e2aed4">XIic_IsSlave()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, <a class="el" href="group___overview.html#ga24873473751e355c82bb074a0d42ddbc">XIic_SlaveSend()</a>, and <a class="el" href="group___overview.html#gaaa989e0128057bf11803825d774d496f">XIic_Stop()</a>.</p>

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          <td class="memname">#define XIIC_SR_RX_FIFO_EMPTY_MASK&#160;&#160;&#160;0x00000040</td>
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<p>1 = Rx FIFO empty </p>

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<p>1 = Rx FIFO full </p>

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          <td class="memname">#define XIIC_SR_TX_FIFO_EMPTY_MASK&#160;&#160;&#160;0x00000080</td>
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<p>1 = Tx FIFO empty </p>

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          <td class="memname">#define XIIC_SR_TX_FIFO_FULL_MASK&#160;&#160;&#160;0x00000010</td>
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<p>1 = Tx FIFO full </p>

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          <td class="memname">#define XIIC_STOP&#160;&#160;&#160;0x00</td>
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<p>The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start. </p>
<p>Send a stop on the IIC bus after the current data transfer </p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="xiic__low__level__dynamic__eeprom__example_8c.html#a50f19b8762ac4b72ca5740da9b4c3690">EepromWriteByte()</a>, and <a class="el" href="xiic__low__level__tempsensor__example_8c.html#ae56cfa9ee65788b4971e0a4d7b32a665">LowLevelTempSensorExample()</a>.</p>

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          <td class="memname">#define XIIC_TBA_REG_OFFSET&#160;&#160;&#160;0x11C</td>
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<p>10 Bit Address reg </p>

<p>Referenced by <a class="el" href="group___overview.html#ga3e8f77e5df8d92a4b27627e03b5e1807">XIic_GetAddress()</a>, and <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress()</a>.</p>

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          <td class="memname">#define XIIC_TFO_REG_OFFSET&#160;&#160;&#160;0x114</td>
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<p>Tx FIFO Occupancy. </p>

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<a class="anchor" id="ga958c3a8926423eed1b2c16aa56938257"></a>
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          <td class="memname">#define XIIC_TX_DYN_START_MASK&#160;&#160;&#160;0x00000100</td>
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<p>1 = Set dynamic start </p>

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<a class="anchor" id="ga7efb5db8358e4ce8fa761d0227f52fba"></a>
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          <td class="memname">#define XIIC_TX_DYN_STOP_MASK&#160;&#160;&#160;0x00000200</td>
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<p>1 = Set dynamic stop </p>

<p>Referenced by <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>.</p>

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          <td class="memname">#define XIIC_TX_INTERRUPTS</td>
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<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a> | <a class="code" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">\</a></div>
<div class="line"><a class="code" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">				 XIIC_INTR_TX_EMPTY_MASK</a> |  <a class="code" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">				 XIIC_INTR_TX_HALF_MASK</a>)</div>
<div class="ttc" id="group___overview_html_gaa1ea99d449fd02f69d41d0f41f093282"><div class="ttname"><a href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a></div><div class="ttdeci">#define XIIC_INTR_TX_ERROR_MASK</div><div class="ttdoc">1 = Tx error/msg complete </div><div class="ttdef"><b>Definition:</b> xiic_l.h:124</div></div>
<div class="ttc" id="group___overview_html_ga4af241dbcd0cb4184fe594d09954f69c"><div class="ttname"><a href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a></div><div class="ttdeci">#define XIIC_INTR_TX_HALF_MASK</div><div class="ttdoc">1 = Tx FIFO half empty </div><div class="ttdef"><b>Definition:</b> xiic_l.h:130</div></div>
<div class="ttc" id="group___overview_html_gadc15e89e891805d58f729c4d1f56b093"><div class="ttname"><a href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a></div><div class="ttdeci">#define XIIC_INTR_TX_EMPTY_MASK</div><div class="ttdoc">1 = Tx FIFO/reg empty </div><div class="ttdef"><b>Definition:</b> xiic_l.h:125</div></div>
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<p>All Tx interrupts commonly used. </p>

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          <td class="memname">#define XIIC_TX_RX_INTERRUPTS&#160;&#160;&#160;(<a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a> | <a class="el" href="group___overview.html#gac9441942c102ac8a8485609d98ba5d5c">XIIC_TX_INTERRUPTS</a>)</td>
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<p>All interrupts commonly used. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>.</p>

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          <td class="memname">#define XIIC_WRITE_OPERATION&#160;&#160;&#160;0</td>
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<p>Write operation on the IIC bus. </p>

<p>Referenced by <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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          <td class="memname">#define XIic_WriteIier</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Enable&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>, (Enable))</td>
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<p>This function sets the contents of the Interrupt Enable Register. </p>
<p>This function writes only the specified value to the register such that some interrupt sources may be enabled and others disabled. It is the caller's responsibility to get the value of the interrupt enable register prior to setting the value to prevent a destructive behavior.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device. </td></tr>
    <tr><td class="paramname">Enable</td><td>is the value to be written to the Interrupt Enable Register. Bit positions of 1 will be enabled. Bit positions of 0 will be disabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga2f926a076e9a6b80bea46664d2e55ee9" title="This function sets the contents of the Interrupt Enable Register. ">XIic_WriteIier(u32 BaseAddress, u32 Enable)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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          <td class="memname">#define XIic_WriteIisr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Status&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group___overview.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>, (Status))</td>
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<p>This function sets the Interrupt status register to the specified value. </p>
<p>This register implements a toggle on write functionality. The interrupt is cleared by writing to this register with the bits to be cleared set to a one and all others to zero. Setting a bit which is zero within this register causes an interrupt to be generated.</p>
<p>This function writes only the specified value to the register such that some status bits may be set and others cleared. It is the caller's responsibility to get the value of the register prior to setting the value to prevent an destructive behavior.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the IIC device. </td></tr>
    <tr><td class="paramname">Status</td><td>is the value to be written to the Interrupt status register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga3bc448908013aceb690c84fdbb7d66a8" title="This function sets the Interrupt status register to the specified value. ">XIic_WriteIisr(u32 BaseAddress, u32 Status)</a>; </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga50c5aa4448e8993c80ef7b6a87b1aaea">XIic_InterruptHandler()</a>.</p>

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          <td class="memname">#define XIic_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegisterValue&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td>
        </tr>
      </table>
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<p>Write to the specified IIC device register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset from the 1st register of the device to select the specific register. </td></tr>
    <tr><td class="paramname">RegisterValue</td><td>is the value to be written to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XIic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 RegisterValue); This macro does not do any checking to ensure that the register exists if the register may be excluded due to parameterization, such as the GPO Register. </dd></dl>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>, <a class="el" href="group___overview.html#ga4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a>, <a class="el" href="group___overview.html#gac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>, <a class="el" href="group___overview.html#ga337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a>, <a class="el" href="group___overview.html#ga977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, <a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset()</a>, <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>, <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297">XIic_SetAddress()</a>, <a class="el" href="group___overview.html#gafe4e886e72abb9d860a6cb83c84c74a1">XIic_SetGpOutput()</a>, <a class="el" href="group___overview.html#ga900a7ab49c2e13b0562ab629c088cf3a">XIic_SetOptions()</a>, <a class="el" href="group___overview.html#ga25dc714d97f71049154461e1ff16bcad">XIic_SlaveRecv()</a>, and <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f">XIic_Start()</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
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          <td class="memname">typedef void(* XIic_Handler)(void *CallBackRef, int ByteCount)</td>
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<p>This callback function data type is defined to handle the asynchronous processing of sent and received data of the IIC driver. </p>
<p>The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handlers are called in an interrupt context such that minimal processing should be performed. The handler data type is utilized for both send and receive handlers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver component, so it is a void pointer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>indicates the number of bytes remaining to be sent or received. A value of zero indicates that the requested number of bytes were sent or received. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">typedef void(* XIic_StatusHandler)(void *CallBackRef, int StatusEvent)</td>
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<p>This callback function data type is defined to handle the asynchronous processing of status events of the IIC driver. </p>
<p>The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler is called in an interrupt context such that minimal processing should be performed.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver component, so it is a void pointer. </td></tr>
    <tr><td class="paramname">StatusEvent</td><td>indicates one or more status events that occurred. See the definition of the status events above. </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">int XIic_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_iic___config.html">XIic_Config</a> *&#160;</td>
          <td class="paramname"><em>Config</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Initializes a specific <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance. </p>
<p>The initialization entails:</p>
<ul>
<li>Initialize the driver to allow access to the device registers and initialize other subcomponents necessary for the operation of the device.</li>
<li>Default options to:<ul>
<li>7-bit slave addressing</li>
<li>Send messages as a slave device</li>
<li>Repeated start off</li>
<li>General call recognition disabled</li>
</ul>
</li>
<li>Clear messageing and error statistics</li>
</ul>
<p>The <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> function must be called after this function before the device is ready to send and receive data on the IIC bus.</p>
<p>Before <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> is called, the interrupt control must connect the ISR routine to the interrupt handler. This is done by the user, and not <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> to allow the user to use an interrupt controller of their choice.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Config</td><td>is a reference to a structure containing information about a specific IIC device. This function can initialize multiple instance objects with the use of multiple calls giving different Config information on each call. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS when successful</li>
<li>XST_DEVICE_IS_STARTED indicates the device is started (i.e. interrupts enabled and messaging is possible). Must stop before re-initialization is allowed.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a309fbb83dcbf11ecb031fc3283c21bd1">XIic::BNBOnly</a>, <a class="el" href="struct_x_iic___config.html#a65ecc64160873e6910dab26b912f437f">XIic_Config::GpOutWidth</a>, <a class="el" href="struct_x_iic.html#a19e2155bd464d4dc9e13d5008e22b404">XIic::GpOutWidth</a>, <a class="el" href="struct_x_iic___config.html#aa0d66ed6f0ba5a65d444a8cff6a2ea40">XIic_Config::Has10BitAddr</a>, <a class="el" href="struct_x_iic.html#a8ab26622cd8ec42dde9515c917a6f5ab">XIic::Has10BitAddr</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="struct_x_iic.html#a85857f85c5a0fc9af74f3a6745839eca">XIic::IsSlaveSetAckOff</a>, <a class="el" href="struct_x_iic.html#add800c0b51a637b186fa8e3b6adf7a7f">XIic::IsStarted</a>, <a class="el" href="struct_x_iic.html#ab975cd4f9408fa6285bc8ba7e030a97a">XIic::Options</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic.html#a6459379a9289a7db0f29ded8c4696e7e">XIic::RecvHandler</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="struct_x_iic.html#aeb346adbf6b1c39840c28e52bb5283e0">XIic::SendHandler</a>, <a class="el" href="struct_x_iic.html#a7e5b8273cb34338759107df1121d03d1">XIic::StatusHandler</a>, <a class="el" href="group___overview.html#gaf56beeeacad67c0d24ad330ce5c42f90">XIic_ClearStats()</a>, and <a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset()</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__selftest__example_8c.html#a224c2ffaa2e5f65cbab83fd243077048">IicSelfTestExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>, and <a class="el" href="group___overview.html#gad36c610ec3139cef71f3795f9ce81308">XIic_Initialize()</a>.</p>

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          <td class="memname">void XIic_ClearStats </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Clears the statistics for the IIC device by zeroing all counts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, and <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga301f08e1fa6e74bf4c2885702bf0ff70">XIic_CfgInitialize()</a>.</p>

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          <td class="memname">int XIic_DynMasterRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>RxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function receives data as a master from a slave device on the IIC bus. </p>
<p>If the bus is busy, it will indicate so and then enable an interrupt such that the status handler will be called when the bus is no longer busy. The slave address which has been set with the <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297" title="This function sets the bus addresses. ">XIic_SetAddress()</a> function is the address from which data is received. Receiving data on the bus performs a read operation.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Iic instance to be worked on. </td></tr>
    <tr><td class="paramname">RxMsgPtr</td><td>is a pointer to the data to be transmitted. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS indicates the message reception processes has been initiated.<ul>
<li>XST_IIC_BUS_BUSY indicates the bus was in use and that the BusNotBusy interrupt is enabled which will update the EventStatus when the bus is no longer busy.</li>
<li>XST_IIC_GENERAL_CALL_ADDRESS indicates the slave address is set to the general call address. This is not allowed for Master receive mode.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The receive FIFO threshold is a zero based count such that 1 must be subtracted from the desired count to get the correct value. When receiving data it is also necessary to not receive the last byte with the prior bytes because the acknowledge must be setup before the last byte is received. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="group___overview.html#ga23db93d1ef8c4651eba08f22fff2ee36">IIC_RX_FIFO_DEPTH</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic.html#ad2cc469bc553fdedcf67a71e36baecb6">XIic::RecvByteCount</a>, <a class="el" href="struct_x_iic_stats.html#a883cabf0999ea6eb384a5ead3b02477c">XIicStats::RepeatedStarts</a>, <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>, <a class="el" href="struct_x_iic.html#ae712d64fa4297ec0ca4792be679c161c">XIic::TxAddrMode</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>, <a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>, <a class="el" href="group___overview.html#ga22446f72b705b950e4b485ab9cdd2ae6">XIic_DynSendStop</a>, <a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a7e1f2a0abc21a277ec8be8199c50169c">DynEepromReadData()</a>.</p>

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          <td class="memname">int XIic_DynMasterSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>TxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sends data as a Dynamic master on the IIC bus. </p>
<p>If the bus is busy, it will indicate so and then enable an interrupt such that the status handler will be called when the bus is no longer busy. The slave address is sent by using <a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b" title="This macro sends the address for a 7 bit address during both read and write operations. ">XIic_DynSend7BitAddress()</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>points to the Iic instance to be worked on. </td></tr>
    <tr><td class="paramname">TxMsgPtr</td><td>points to the data to be transmitted. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS if successful else XST_FAILURE.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic_stats.html#a883cabf0999ea6eb384a5ead3b02477c">XIicStats::RepeatedStarts</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="struct_x_iic.html#a754131dbb0faeda957f6124df82eecf0">XIic::SendByteCount</a>, <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>, <a class="el" href="struct_x_iic.html#ae712d64fa4297ec0ca4792be679c161c">XIic::TxAddrMode</a>, <a class="el" href="group___overview.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">XIIC_MASTER_ROLE</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a4a76229cbb6ce631f3271eb592b69d0f">DynEepromWriteData()</a>.</p>

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          <td class="memname">unsigned XIic_DynRecv </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Address</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>BufferPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Receive data as a master on the IIC bus. </p>
<p>This function receives the data using polled I/O and blocks until the data has been received. It only supports 7 bit addressing. This function returns zero if bus is busy.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">Address</td><td>contains the 7 bit IIC Device address of the device to send the specified data to. </td></tr>
    <tr><td class="paramname">BufferPtr</td><td>points to the data to be sent. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent. This value can't be greater than 255 and needs to be greater than 0.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes received.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Upon entry to this function, the IIC interface needs to be already enabled in the CR register. </dd></dl>

<p>References <a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>, <a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>, <a class="el" href="group___overview.html#ga22446f72b705b950e4b485ab9cdd2ae6">XIic_DynSendStop</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree()</a>.</p>

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          <td class="memname">unsigned XIic_DynSend </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Address</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>BufferPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ByteCount</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Option</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Send data as a master on the IIC bus. </p>
<p>This function sends the data using polled I/O and blocks until the data has been sent. It only supports 7 bit addressing. This function returns zero if bus is busy.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the IIC Device. </td></tr>
    <tr><td class="paramname">Address</td><td>contains the 7 bit IIC address of the device to send the specified data to. </td></tr>
    <tr><td class="paramname">BufferPtr</td><td>points to the data to be sent. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent. </td></tr>
    <tr><td class="paramname">Option,:</td><td>XIIC_STOP = end with STOP condition, XIIC_REPEATED_START = don't end with STOP condition.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes sent.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>, <a class="el" href="group___overview.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>, <a class="el" href="group___overview.html#ga682d21ed5020daa5b5a863bbffb35cc5">XIic_DynSendStartStopAddress</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a>, <a class="el" href="group___overview.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree()</a>, and <a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>.</p>

<p>Referenced by <a class="el" href="xiic__low__level__dynamic__eeprom__example_8c.html#a50f19b8762ac4b72ca5740da9b4c3690">EepromWriteByte()</a>.</p>

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          <td class="memname">u16 XIic_GetAddress </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>AddressType</em>&#160;</td>
        </tr>
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          <td></td>
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<p>This function gets the addresses for the IIC device driver. </p>
<p>The addresses include the device address that the device responds to as a slave, or the slave address to communicate with on the bus. The address returned has the same format whether 7 or 10 bits.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">AddressType</td><td>indicates which address, the address which this responds to on the IIC bus as a slave, or the slave address to communicate with when this device is a master. One of the following values must be contained in this argument. <pre>
  XII_ADDR_TO_SEND_TYPE Slave being addressed as a master
  XII_ADDR_TO_RESPOND_TYPE      Slave address to respond to as a slave
</pre> If neither of the two valid arguments are used, the function returns the address of the slave device</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The address retrieved.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a8ab26622cd8ec42dde9515c917a6f5ab">XIic::Has10BitAddr</a>, <a class="el" href="group___overview.html#gab3f6ec08afcad8f35f9ee2c9e2531366">XII_ADDR_TO_RESPOND_TYPE</a>, <a class="el" href="group___overview.html#ga831a9fbdcfebad501e336231321be40a">XIIC_ADR_REG_OFFSET</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, and <a class="el" href="group___overview.html#gaf50b1672278bdf573cd74e36768b0cda">XIIC_TBA_REG_OFFSET</a>.</p>

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          <td class="memname">int XIic_GetGpOutput </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>OutputValuePtr</em>&#160;</td>
        </tr>
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<p>This function gets the contents of the General Purpose Output register for the IIC device driver. </p>
<p>Note that the number of bits in this register is parameterizable in the hardware such that it may not exist. This function checks to ensure that it does exist to prevent bus errors.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">OutputValuePtr</td><td>contains the value which was read from the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the given data is read from the GPO register.<ul>
<li>XST_NO_FEATURE if the hardware is configured such that this register does not contain any bits to read or write.</li>
</ul>
</li>
</ul>
</dd></dl>
<p>The OutputValuePtr is also an output as it contains the value read.</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a19e2155bd464d4dc9e13d5008e22b404">XIic::GpOutWidth</a>, <a class="el" href="group___overview.html#gaf901951024f3144cd51ce84d897a5f5b">XIIC_GPO_REG_OFFSET</a>, and <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>.</p>

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          <td class="memname">u32 XIic_GetOptions </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function gets the current options for the IIC device. </p>
<p>Options control the how the device behaves on the IIC bus. See SetOptions for more information on options.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The options of the IIC device. See <a class="el" href="xiic_8h.html">xiic.h</a> for a list of available options.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>Options enabled will have a 1 in its appropriate bit position. </p>

<p>References <a class="el" href="struct_x_iic.html#ab975cd4f9408fa6285bc8ba7e030a97a">XIic::Options</a>.</p>

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          <td class="memname">void XIic_GetStats </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_iic_stats.html">XIicStats</a> *&#160;</td>
          <td class="paramname"><em>StatsPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Gets a copy of the statistics for an IIC device. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">StatsPtr</td><td>is a pointer to a <a class="el" href="struct_x_iic_stats.html" title="XIic statistics. ">XIicStats</a> structure which will get a copy of current statistics.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, and <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>.</p>

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          <td class="memname">int XIic_Initialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Initializes a specific <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance. </p>
<p>The initialization entails:</p>
<ul>
<li>Check the device has an entry in the configuration table.</li>
<li>Initialize the driver to allow access to the device registers and initialize other subcomponents necessary for the operation of the device.</li>
<li>Default options to:<ul>
<li>7-bit slave addressing</li>
<li>Send messages as a slave device</li>
<li>Repeated start off</li>
<li>General call recognition disabled</li>
</ul>
</li>
<li>Clear messageing and error statistics</li>
</ul>
<p>The <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> function must be called after this function before the device is ready to send and receive data on the IIC bus.</p>
<p>Before <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> is called, the interrupt control must connect the ISR routine to the interrupt handler. This is done by the user, and not <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> to allow the user to use an interrupt controller of their choice.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">DeviceId</td><td>is the unique id of the device controlled by this <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance. Passing in a device id associates the generic <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to a specific device, as chosen by the caller or application developer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS when successful</li>
<li>XST_DEVICE_NOT_FOUND indicates the given device id isn't found</li>
<li>XST_DEVICE_IS_STARTED indicates the device is started (i.e. interrupts enabled and messaging is possible). Must stop before re-initialization is allowed.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic___config.html#ae783f76b6713be6d9b77060d77328102">XIic_Config::BaseAddress</a>, <a class="el" href="group___overview.html#ga301f08e1fa6e74bf4c2885702bf0ff70">XIic_CfgInitialize()</a>, and <a class="el" href="group___overview.html#ga1dcc65dd7cb7863bf6769aed5d785304">XIic_LookupConfig()</a>.</p>

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          <td class="memname">void XIic_InterruptHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function is the interrupt handler for the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> driver. </p>
<p>This function should be connected to the interrupt system.</p>
<p>Only one interrupt source is handled for each interrupt allowing higher priority system interrupts quicker response time.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic_stats.html#a8dd8285757503a00e678eba64ba60713">XIicStats::ArbitrationLost</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a309fbb83dcbf11ecb031fc3283c21bd1">XIic::BNBOnly</a>, <a class="el" href="struct_x_iic_stats.html#a029e0c1dd27db0a22e07c79d158db149">XIicStats::IicInterrupts</a>, <a class="el" href="struct_x_iic.html#ad2cc469bc553fdedcf67a71e36baecb6">XIic::RecvByteCount</a>, <a class="el" href="struct_x_iic_stats.html#a1e4c261ba880898121d01fef25272640">XIicStats::RecvInterrupts</a>, <a class="el" href="struct_x_iic.html#a42ba7a5a3635caf03b7e15fa3348b32f">XIic::SendCallBackRef</a>, <a class="el" href="struct_x_iic.html#aeb346adbf6b1c39840c28e52bb5283e0">XIic::SendHandler</a>, <a class="el" href="struct_x_iic_stats.html#a91c185703ed112b39723e7141f33c760">XIicStats::SendInterrupts</a>, <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>, <a class="el" href="struct_x_iic_stats.html#a35580c344011980f77137d9957a8e308">XIicStats::TxErrors</a>, <a class="el" href="group___overview.html#ga88cf05913ad5693c477993c2af6cbd7e">XIIC_INTR_AAS_MASK</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>, <a class="el" href="group___overview.html#gab153bb7f21133bf7471c70f4089494a5">XIIC_INTR_NAAS_MASK</a>, <a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>, <a class="el" href="group___overview.html#gaa839067df3b55f3181db24ebd8db3187">XIic_IsIntrGlobalEnabled</a>, <a class="el" href="group___overview.html#gaee17ffc86a8270abeb1319e8c67ccce5">XIic_ReadIier</a>, <a class="el" href="group___overview.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, and <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>.</p>

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          <td class="memname">u32 XIic_IsSlave </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>A function to determine if the device is currently addressed as a slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if the device is addressed as slave.</li>
</ul>
</dd></dl>
<ul>
<li>FALSE if the device is NOT addressed as slave.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, and <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_iic___config.html">XIic_Config</a> * XIic_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
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<p>Looks up the device configuration based on the unique device ID. </p>
<p>The table IicConfigTable contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID to look for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the configuration data of the device, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group___overview.html#gabf1a99c517996564a1bfa7ccecd1e6f5">XIic_ConfigTable</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__selftest__example_8c.html#a224c2ffaa2e5f65cbab83fd243077048">IicSelfTestExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>, and <a class="el" href="group___overview.html#gad36c610ec3139cef71f3795f9ce81308">XIic_Initialize()</a>.</p>

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          <td class="memname">int XIic_MasterRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>RxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function receives data as a master from a slave device on the IIC bus. </p>
<p>If the bus is busy, it will indicate so and then enable an interrupt such that the status handler will be called when the bus is no longer busy. The slave address which has been set with the <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297" title="This function sets the bus addresses. ">XIic_SetAddress()</a> function is the address from which data is received. Receiving data on the bus performs a read operation.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Iic instance to be worked on. </td></tr>
    <tr><td class="paramname">RxMsgPtr</td><td>is a pointer to the data to be transmitted </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS indicates the message reception processes has been initiated.</li>
<li>XST_IIC_BUS_BUSY indicates the bus was in use and that the BusNotBusy interrupt is enabled which will update the EventStatus when the bus is no longer busy.</li>
<li>XST_IIC_GENERAL_CALL_ADDRESS indicates the slave address is set to the the general call address. This is not allowed for Master receive mode. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="group___overview.html#ga23db93d1ef8c4651eba08f22fff2ee36">IIC_RX_FIFO_DEPTH</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic.html#ab975cd4f9408fa6285bc8ba7e030a97a">XIic::Options</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic.html#ad2cc469bc553fdedcf67a71e36baecb6">XIic::RecvByteCount</a>, <a class="el" href="struct_x_iic_stats.html#a883cabf0999ea6eb384a5ead3b02477c">XIicStats::RepeatedStarts</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>, <a class="el" href="struct_x_iic.html#ae712d64fa4297ec0ca4792be679c161c">XIic::TxAddrMode</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>, <a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__eeprom__example_8c.html#a72f47aa22ac802f95eaec2691bf7ccb5">EepromReadData()</a>, and <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>.</p>

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          <td class="memname">int XIic_MasterSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>TxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sends data as a master on the IIC bus. </p>
<p>If the bus is busy, it will indicate so and then enable an interrupt such that the status handler will be called when the bus is no longer busy. The slave address which has been set with the <a class="el" href="group___overview.html#gad944f42c3d9972fc2c986a7eed726297" title="This function sets the bus addresses. ">XIic_SetAddress()</a> function is the address to which the specific data is sent. Sending data on the bus performs a write operation.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>points to the Iic instance to be worked on. </td></tr>
    <tr><td class="paramname">TxMsgPtr</td><td>points to the data to be transmitted. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS indicates the message transmission has been initiated.</li>
<li>XST_IIC_BUS_BUSY indicates the bus was in use and that the BusNotBusy interrupt is enabled which will update the EventStatus when the bus is no longer busy.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic.html#ab975cd4f9408fa6285bc8ba7e030a97a">XIic::Options</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic_stats.html#a883cabf0999ea6eb384a5ead3b02477c">XIicStats::RepeatedStarts</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="struct_x_iic.html#a754131dbb0faeda957f6124df82eecf0">XIic::SendByteCount</a>, <a class="el" href="struct_x_iic.html#a823a2f7407e2c6990f1eb507ea742e85">XIic::Stats</a>, <a class="el" href="struct_x_iic.html#ae712d64fa4297ec0ca4792be679c161c">XIic::TxAddrMode</a>, <a class="el" href="group___overview.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">XIIC_MASTER_ROLE</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a4a76229cbb6ce631f3271eb592b69d0f">DynEepromWriteData()</a>, <a class="el" href="xiic__eeprom__example_8c.html#a40d92867ead2dc8efe06207b8b0f3494">EepromWriteData()</a>, and <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>.</p>

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          <td class="memname">void XIic_MultiMasterInclude </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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<p>This function includes multi-master code such that multi-master events are handled properly. </p>
<p>Multi-master events include a loss of arbitration and the bus transitioning from busy to not busy. This function allows the multi-master processing to be optional. This function must be called prior to allowing any multi-master events to occur, such as after the driver is initialized.</p>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>.</p>

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          <td class="memname">unsigned XIic_Recv </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Address</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>BufferPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned&#160;</td>
          <td class="paramname"><em>ByteCount</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Option</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Receive data as a master on the IIC bus. </p>
<p>This function receives the data using polled I/O and blocks until the data has been received. It only supports 7 bit addressing mode of operation. This function returns zero if bus is busy.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the IIC device. </td></tr>
    <tr><td class="paramname">Address</td><td>contains the 7 bit IIC address of the device to send the specified data to. </td></tr>
    <tr><td class="paramname">BufferPtr</td><td>points to the data to be sent. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent. </td></tr>
    <tr><td class="paramname">Option</td><td>indicates whether to hold or free the bus after reception of data, XIIC_STOP = end with STOP condition, XIIC_REPEATED_START = don't end with STOP condition.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes received.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>, <a class="el" href="group___overview.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>, <a class="el" href="group___overview.html#gaa4fa9698cb076131f2d4571ef3bae6f3">XIIC_CR_ENABLE_DEVICE_MASK</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>, <a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga89d095e79795958bcbc15238a7bbfa32">XIic_Send7BitAddress</a>, <a class="el" href="group___overview.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree()</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, and <a class="el" href="xiic__low__level__tempsensor__example_8c.html#ae56cfa9ee65788b4971e0a4d7b32a665">LowLevelTempSensorExample()</a>.</p>

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          <td class="memname">void XIic_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Resets the IIC device. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The complete IIC core is Reset on giving a software reset to the IIC core. Some previous versions of the core only reset the Interrupt Logic/Registers, please refer to the HW specification for further details about this. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="group___overview.html#gad29589acad66518bac5f21a670ccc9a5">XIIC_RESET_MASK</a>, <a class="el" href="group___overview.html#ga2129f15b6d659403e4aa18355aa67884">XIIC_RESETR_OFFSET</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga301f08e1fa6e74bf4c2885702bf0ff70">XIic_CfgInitialize()</a>, and <a class="el" href="group___overview.html#ga0a4d9b646c26bcf932561699d69d52b1">XIic_SelfTest()</a>.</p>

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          <td class="memname">int XIic_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>Runs a limited self-test on the driver/device. </p>
<p>This test does a read/write test of the Interrupt Registers There is no loopback capabilities for the device such that this test does not send or receive data.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if no errors are found</li>
<li>XST_FAILURE if errors are found</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gaa839067df3b55f3181db24ebd8db3187">XIic_IsIntrGlobalEnabled</a>, <a class="el" href="group___overview.html#gaee17ffc86a8270abeb1319e8c67ccce5">XIic_ReadIier</a>, <a class="el" href="group___overview.html#ga237935ed7fb41369f52d1d8a4f6fe2a6">XIic_Reset()</a>, <a class="el" href="group___overview.html#gac942198f619f45e2705457967e1683c8">XIIC_TX_RX_INTERRUPTS</a>, and <a class="el" href="group___overview.html#ga2f926a076e9a6b80bea46664d2e55ee9">XIic_WriteIier</a>.</p>

<p>Referenced by <a class="el" href="xiic__selftest__example_8c.html#a224c2ffaa2e5f65cbab83fd243077048">IicSelfTestExample()</a>.</p>

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          <td class="memname">unsigned XIic_Send </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Address</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>BufferPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned&#160;</td>
          <td class="paramname"><em>ByteCount</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Option</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Send data as a master on the IIC bus. </p>
<p>This function sends the data using polled I/O and blocks until the data has been sent. It only supports 7 bit addressing mode of operation. This function returns zero if bus is busy.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the IIC device. </td></tr>
    <tr><td class="paramname">Address</td><td>contains the 7 bit IIC address of the device to send the specified data to. </td></tr>
    <tr><td class="paramname">BufferPtr</td><td>points to the data to be sent. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent. </td></tr>
    <tr><td class="paramname">Option</td><td>indicates whether to hold or free the bus after transmitting the data.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes sent.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group___overview.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>, <a class="el" href="group___overview.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>, <a class="el" href="group___overview.html#gaa4fa9698cb076131f2d4571ef3bae6f3">XIIC_CR_ENABLE_DEVICE_MASK</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga89d095e79795958bcbc15238a7bbfa32">XIic_Send7BitAddress</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, <a class="el" href="group___overview.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree()</a>, <a class="el" href="group___overview.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__low__level__eeprom__example_8c.html#a5c87929a9d1ad69044b17cde4cf03c0a">EepromReadByte()</a>, and <a class="el" href="xiic__low__level__eeprom__example_8c.html#a16a37ddca6337489a7c9deadddfc1547">EepromWriteByte()</a>.</p>

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          <td class="memname">int XIic_SetAddress </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>AddressType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Address</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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<p>This function sets the bus addresses. </p>
<p>The addresses include the device address that the device responds to as a slave, or the slave address to communicate with on the bus. The IIC device hardware is built to allow either 7 or 10 bit slave addressing only at build time rather than at run time. When this device is a master, slave addressing can be selected at run time to match addressing modes for other bus devices.</p>
<p>Addresses are represented as hex values with no adjustment for the data direction bit as the software manages address bit placement. Example: For a 7 address written to the device of 1010 011X where X is the transfer direction (send/recv), the address parameter for this function needs to be 01010011 or 0x53 where the correct bit alllignment will be handled for 7 as well as 10 bit devices. This is especially important as the bit placement is not handled the same depending on which options are used such as repeated start.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">AddressType</td><td>indicates which address is being modified, the address which this device responds to on the IIC bus as a slave, or the slave address to communicate with when this device is a master. One of the following values must be contained in this argument. <pre>
  XII_ADDR_TO_SEND_TYPE Slave being addressed by a this master
  XII_ADDR_TO_RESPOND_TYPE      Address to respond to as a slave device
</pre></td></tr>
    <tr><td class="paramname">Address</td><td>contains the address to be set, 7 bit or 10 bit address. A ten bit address must be within the range: 0 - 1023 and a 7 bit address must be within the range 0 - 127.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS is returned if the address was successfully set.</li>
<li>XST_IIC_NO_10_BIT_ADDRESSING indicates only 7 bit addressing supported.</li>
<li>XST_INVALID_PARAM indicates an invalid parameter was specified.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>Upper bits of 10-bit address is written only when current device is built as a ten bit device. </p>

<p>References <a class="el" href="struct_x_iic.html#ac8791f24ad6311a916cedb2ebd6b3774">XIic::AddrOfSlave</a>, <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a8ab26622cd8ec42dde9515c917a6f5ab">XIic::Has10BitAddr</a>, <a class="el" href="group___overview.html#gab3f6ec08afcad8f35f9ee2c9e2531366">XII_ADDR_TO_RESPOND_TYPE</a>, <a class="el" href="group___overview.html#gace6af337aea33e4f162897b40591e0ac">XII_ADDR_TO_SEND_TYPE</a>, <a class="el" href="group___overview.html#ga831a9fbdcfebad501e336231321be40a">XIIC_ADR_REG_OFFSET</a>, <a class="el" href="group___overview.html#gaf50b1672278bdf573cd74e36768b0cda">XIIC_TBA_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, and <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>.</p>

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          <td class="memname">int XIic_SetGpOutput </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>OutputValue</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sets the contents of the General Purpose Output register for the IIC device driver. </p>
<p>Note that the number of bits in this register is parameterizable in the hardware such that it may not exist. This function checks to ensure that it does exist to prevent bus errors, but does not ensure that the number of bits in the register are sufficient for the value being written (won't cause a bus error).</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">OutputValue</td><td>contains the value to be written to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the given data is written to the GPO register.<ul>
<li>XST_NO_FEATURE if the hardware is configured such that this register does not contain any bits to read or write.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#a19e2155bd464d4dc9e13d5008e22b404">XIic::GpOutWidth</a>, <a class="el" href="group___overview.html#gaf901951024f3144cd51ce84d897a5f5b">XIIC_GPO_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

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          <td class="memname">void XIic_SetOptions </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>NewOptions</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function sets the options for the IIC device driver. </p>
<p>The options control how the device behaves relative to the IIC bus. If an option applies to how messages are sent or received on the IIC bus, it must be set prior to calling functions which send or receive data.</p>
<p>To set multiple options, the values must be ORed together. To not change existing options, read/modify/write with the current options using <a class="el" href="group___overview.html#gaf15dd70c4f1bb34a9e35c1ca85cee841" title="This function gets the current options for the IIC device. ">XIic_GetOptions()</a>.</p>
<p><b>USAGE EXAMPLE:</b></p>
<p>Read/modify/write to enable repeated start: </p>
<pre>
  u8 Options;
  Options = XIic_GetOptions(&amp;Iic);
  XIic_SetOptions(&amp;Iic, Options | XII_REPEATED_START_OPTION);
</pre><p>Disabling General Call: </p>
<pre>
  Options = XIic_GetOptions(&amp;Iic);
  XIic_SetOptions(&amp;Iic, Options &amp;= ~XII_GENERAL_CALL_OPTION);
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">NewOptions</td><td>are the options to be set. See <a class="el" href="xiic_8h.html">xiic.h</a> for a list of the available options.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>Sending or receiving messages with repeated start enabled, and then disabling repeated start, will not take effect until another master transaction is completed. i.e. After using repeated start, the bus will continue to be throttled after repeated start is disabled until a master transaction occurs allowing the IIC to release the bus. <br/>
<br/>
 Options enabled will have a 1 in its appropriate bit position. </p>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#ab975cd4f9408fa6285bc8ba7e030a97a">XIic::Options</a>, <a class="el" href="group___overview.html#ga44d0ebf5153203223cb5563aaa10a301">XII_GENERAL_CALL_OPTION</a>, <a class="el" href="group___overview.html#gac9dda6b07f8f4d2962b8833b05b8603b">XIIC_CR_GENERAL_CALL_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>.</p>

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          <td class="memname">void XIic_SetRecvHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group___overview.html#ga85db866c44d23a4c6e985f2c6c647053">XIic_Handler</a>&#160;</td>
          <td class="paramname"><em>FuncPtr</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Sets the receive callback function, the receive handler, which the driver calls when it finishes receiving data. </p>
<p>The number of bytes used to signal when the receive is complete is the number of bytes set in the XIic_Recv function.</p>
<p>The handler executes in an interrupt context such that it must minimize the amount of processing performed such as transferring data to a thread context.</p>
<p>The number of bytes received is passed to the handler as an argument.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the upper layer callback reference passed back when the callback function is invoked. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>is the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The handler is called within interrupt context . </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="struct_x_iic.html#a089dc79200a64984f2fc5dca2b3a0ab5">XIic::RecvCallBackRef</a>, and <a class="el" href="struct_x_iic.html#a6459379a9289a7db0f29ded8c4696e7e">XIic::RecvHandler</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, and <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>.</p>

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          <td class="memname">void XIic_SetSendHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group___overview.html#ga85db866c44d23a4c6e985f2c6c647053">XIic_Handler</a>&#160;</td>
          <td class="paramname"><em>FuncPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Sets the send callback function, the send handler, which the driver calls when it receives confirmation of sent data. </p>
<p>The handler executes in an interrupt context such that it must minimize the amount of processing performed such as transferring data to a thread context.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>the pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>the upper layer callback reference passed back when the callback function is invoked. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The handler is called within interrupt context . </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="struct_x_iic.html#a42ba7a5a3635caf03b7e15fa3348b32f">XIic::SendCallBackRef</a>, and <a class="el" href="struct_x_iic.html#aeb346adbf6b1c39840c28e52bb5283e0">XIic::SendHandler</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>.</p>

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          <td class="memname">void XIic_SetStatusHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group___overview.html#gac96e3f6975be1bdb8fe5956812855962">XIic_StatusHandler</a>&#160;</td>
          <td class="paramname"><em>FuncPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Sets the status callback function, the status handler, which the driver calls when it encounters conditions which are not data related. </p>
<p>The handler executes in an interrupt context such that it must minimize the amount of processing performed such as transferring data to a thread context. The status events that can be returned are described in <a class="el" href="xiic_8h.html">xiic.h</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>points to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the upper layer callback reference passed back when the callback function is invoked. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>is the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The handler is called within interrupt context . </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="struct_x_iic.html#a97be26eed0e2551b19c3a296c1c20909">XIic::StatusCallBackRef</a>, and <a class="el" href="struct_x_iic.html#a7e5b8273cb34338759107df1121d03d1">XIic::StatusHandler</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#acf73440d825599aa965a161279937fdb">IicDynEepromExample()</a>, <a class="el" href="xiic__eeprom__example_8c.html#aa0f15e4ae2ab31c19f1268a81acdfe23">IicEepromExample()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__repeated__start__example_8c.html#ad711cc13c49a8ea279600d27dd1148c1">IicRepeatedStartExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>, and <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>.</p>

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          <td class="memname">void XIic_SlaveInclude </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function includes slave code such that slave events will be processed. </p>
<p>It is necessary to allow slave code to be optional to reduce the size of the driver. This function may be called at any time but must be prior to being selected as a slave on the IIC bus. This function may be called prior to the Cfg_Initialize() function and must be called before any functions in this file are called.</p>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a7f5dc26ef1947d1825780346d26d5f70">IicSlaveExample()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#ab4e612135486e268a4db49b75f625f52">IicTenBitAddrExample()</a>.</p>

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          <td class="memname">int XIic_SlaveRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>RxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sends data as a slave on the IIC bus and should not be called until an event has occurred that indicates the device has been selected by a master attempting read from the slave (XII_MASTER_READ_EVENT). </p>
<p>If more data is received than specified a No Acknowledge will be sent to signal the Master to stop sending data. Any received data is read to prevent the slave device from throttling the bus.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Iic instance to be worked on. </td></tr>
    <tr><td class="paramname">RxMsgPtr</td><td>is a pointer to the data to be transmitted. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS indicates the message transmission has been initiated.</li>
<li>XST_IIC_NOT_SLAVE indicates the device has not been selected to be a slave on the IIC bus such that data cannot be received. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="group___overview.html#ga23db93d1ef8c4651eba08f22fff2ee36">IIC_RX_FIFO_DEPTH</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic.html#ad2cc469bc553fdedcf67a71e36baecb6">XIic::RecvByteCount</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="group___overview.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a91e062862cf2b2bf6c6f8120baa882be">SlaveReadData()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#adc9d7e63c6a7961710a9ae7df6b824d7">TenBitAddrReadData()</a>.</p>

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          <td class="memname">int XIic_SlaveSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>TxMsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sends data as a slave on the IIC bus and should not be called until an event has occurred that indicates the device has been selected by a master attempting read from the slave (XII_MASTER_READ_EVENT). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">TxMsgPtr</td><td>is a pointer to the data to be transmitted. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of message bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS indicates the message transmission has been initiated.</li>
<li>XST_IIC_NOT_SLAVE indicates the device has not been selected to be a slave on the IIC bus such that data cannot be sent.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#aa962aaf40d5fb305ae9cca9bb00ac4ca">XIic::RecvBufferPtr</a>, <a class="el" href="struct_x_iic.html#afcc1aa70319f4a9676b02f9f019b76b5">XIic::SendBufferPtr</a>, <a class="el" href="struct_x_iic.html#a754131dbb0faeda957f6124df82eecf0">XIic::SendByteCount</a>, <a class="el" href="group___overview.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>, <a class="el" href="group___overview.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#ga85bbbc139ce96e43b2f1f947d0652539">XIIC_SLAVE_ROLE</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, and <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xiic__slave__example_8c.html#a0f41d940d34ed71035e6f6aeb24bdf67">SlaveWriteData()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#a2e451cd59da6f2b702a42a4fcb21a362">TenBitAddrWriteData()</a>.</p>

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          <td class="memname">int XIic_Start </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function starts the IIC device and driver by enabling the proper interrupts such that data may be sent and received on the IIC bus. </p>
<p>This function must be called before the functions to send and receive data.</p>
<p>Before <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> is called, the interrupt control must connect the ISR routine to the interrupt handler. This is done by the user, and not <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> to allow the user to use an interrupt controller of their choice.</p>
<p>Start enables:</p>
<ul>
<li>IIC device</li>
<li>Interrupts:<ul>
<li>Addressed as slave to allow messages from another master</li>
<li>Arbitration Lost to detect Tx arbitration errors</li>
<li>Global IIC interrupt</li>
</ul>
</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS always.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>The device interrupt is connected to the interrupt controller, but no "messaging" interrupts are enabled. Addressed as Slave is enabled to reception of messages when this devices address is written to the bus. The correct messaging interrupts are enabled when sending or receiving via the IicSend() and IicRecv() functions. No action is required by the user to control any IIC interrupts as the driver completely manages all 8 interrupts. Start and Stop control the ability to use the device. Stopping the device completely stops all device interrupts from the processor. </p>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#abf2872ae10b1c7faf6256e6691ff46af">XIic::IsDynamic</a>, <a class="el" href="struct_x_iic.html#ae84af1d59d6e5339a26045e730f0cbde">XIic::IsReady</a>, <a class="el" href="struct_x_iic.html#add800c0b51a637b186fa8e3b6adf7a7f">XIic::IsStarted</a>, <a class="el" href="group___overview.html#gaa4fa9698cb076131f2d4571ef3bae6f3">XIIC_CR_ENABLE_DEVICE_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga88cf05913ad5693c477993c2af6cbd7e">XIIC_INTR_AAS_MASK</a>, <a class="el" href="group___overview.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga2f926a076e9a6b80bea46664d2e55ee9">XIic_WriteIier</a>, and <a class="el" href="group___overview.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a7e1f2a0abc21a277ec8be8199c50169c">DynEepromReadData()</a>, <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a4a76229cbb6ce631f3271eb592b69d0f">DynEepromWriteData()</a>, <a class="el" href="xiic__eeprom__example_8c.html#a72f47aa22ac802f95eaec2691bf7ccb5">EepromReadData()</a>, <a class="el" href="xiic__eeprom__example_8c.html#a40d92867ead2dc8efe06207b8b0f3494">EepromWriteData()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a91e062862cf2b2bf6c6f8120baa882be">SlaveReadData()</a>, <a class="el" href="xiic__slave__example_8c.html#a0f41d940d34ed71035e6f6aeb24bdf67">SlaveWriteData()</a>, <a class="el" href="xiic__tempsensor__example_8c.html#aac3cf14851d8400443fc92099624f671">TempSensorExample()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#adc9d7e63c6a7961710a9ae7df6b824d7">TenBitAddrReadData()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#a2e451cd59da6f2b702a42a4fcb21a362">TenBitAddrWriteData()</a>.</p>

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          <td class="memname">int XIic_Stop </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_iic.html">XIic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function stops the IIC device and driver such that data is no longer sent or received on the IIC bus. </p>
<p>This function stops the device by disabling interrupts. This function only disables interrupts within the device such that the caller is responsible for disconnecting the interrupt handler of the device from the interrupt source and disabling interrupts at other levels.</p>
<p>Due to bus throttling that could hold the bus between messages when using repeated start option, stop will not occur when the device is actively sending or receiving data from the IIC bus or the bus is being throttled by this device, but instead return XST_IIC_BUS_BUSY.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS indicates all IIC interrupts are disabled. No messages can be received or transmitted until <a class="el" href="group___overview.html#ga5f4e497710a9c3719f27d40faa74a10f" title="This function starts the IIC device and driver by enabling the proper interrupts such that data may b...">XIic_Start()</a> is called.</li>
<li>XST_IIC_BUS_BUSY indicates this device is currently engaged in message traffic and cannot be stopped.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_iic.html#a389e4b8500329c37d7835098408b5ed3">XIic::BaseAddress</a>, <a class="el" href="struct_x_iic.html#add800c0b51a637b186fa8e3b6adf7a7f">XIic::IsStarted</a>, <a class="el" href="group___overview.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>, <a class="el" href="group___overview.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>, <a class="el" href="group___overview.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>, <a class="el" href="group___overview.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>, <a class="el" href="group___overview.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>, <a class="el" href="group___overview.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>, and <a class="el" href="group___overview.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a7e1f2a0abc21a277ec8be8199c50169c">DynEepromReadData()</a>, <a class="el" href="xiic__dynamic__eeprom__example_8c.html#a4a76229cbb6ce631f3271eb592b69d0f">DynEepromWriteData()</a>, <a class="el" href="xiic__eeprom__example_8c.html#a72f47aa22ac802f95eaec2691bf7ccb5">EepromReadData()</a>, <a class="el" href="xiic__eeprom__example_8c.html#a40d92867ead2dc8efe06207b8b0f3494">EepromWriteData()</a>, <a class="el" href="xiic__multi__master__example_8c.html#a1910a4a03c18e6dcc001ad0880af0782">IicMultiMasterExample()</a>, <a class="el" href="xiic__slave__example_8c.html#a91e062862cf2b2bf6c6f8120baa882be">SlaveReadData()</a>, <a class="el" href="xiic__slave__example_8c.html#a0f41d940d34ed71035e6f6aeb24bdf67">SlaveWriteData()</a>, <a class="el" href="xiic__tenbitaddr__example_8c.html#adc9d7e63c6a7961710a9ae7df6b824d7">TenBitAddrReadData()</a>, and <a class="el" href="xiic__tenbitaddr__example_8c.html#a2e451cd59da6f2b702a42a4fcb21a362">TenBitAddrWriteData()</a>.</p>

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          <td class="memname">u32 XIic_WaitBusFree </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function will wait until the I2C bus is free or timeout. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the I2C device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the I2C bus was freed before the timeout.</li>
<li>XST_FAILURE otherwise.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv()</a>, <a class="el" href="group___overview.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend()</a>, <a class="el" href="group___overview.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv()</a>, and <a class="el" href="group___overview.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send()</a>.</p>

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<h2 class="groupheader">Variable Documentation</h2>
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          <td class="memname"><a class="el" href="struct_x_iic___config.html">XIic_Config</a> XIic_ConfigTable[XPAR_XIIC_NUM_INSTANCES]</td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Initial value:</b><div class="fragment"><div class="line">= {</div>
<div class="line">        {</div>
<div class="line">         XPAR_IIC_0_DEVICE_ID,  </div>
<div class="line">         XPAR_IIC_0_BASEADDR,   </div>
<div class="line">         XPAR_IIC_0_TEN_BIT_ADR,</div>
<div class="line">         XPAR_IIC_0_GPO_WIDTH   </div>
<div class="line">        }</div>
<div class="line">        ,</div>
<div class="line">        {</div>
<div class="line">         XPAR_IIC_1_DEVICE_ID,  </div>
<div class="line">         XPAR_IIC_1_BASEADDR,   </div>
<div class="line">         XPAR_IIC_1_TEN_BIT_ADR, </div>
<div class="line">         XPAR_IIC_1_GPO_WIDTH   </div>
<div class="line">        }</div>
<div class="line">}</div>
</div><!-- fragment -->
<p>The IIC configuration table, sized by the number of instances defined in xparameters.h. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga1dcc65dd7cb7863bf6769aed5d785304">XIic_LookupConfig()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_iic___config.html">XIic_Config</a> XIic_ConfigTable[]</td>
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<p>The IIC configuration table, sized by the number of instances defined in xparameters.h. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga1dcc65dd7cb7863bf6769aed5d785304">XIic_LookupConfig()</a>.</p>

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